Lines Matching +full:tx +full:- +full:termination +full:- +full:fix
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
20 #include <linux/dma-mapping.h>
23 #include <media/cec-notifier.h>
25 #include <linux/media-bus-format.h>
39 #include "dw-hdmi-audio.h"
40 #include "dw-hdmi-cec.h"
41 #include "dw-hdmi.h"
48 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
169 enum drm_connector_force force; /* mutex-protected force state */
210 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
217 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
224 if (hdmi->plugged_cb && hdmi->codec_dev)
225 hdmi->plugged_cb(hdmi->codec_dev, plugged);
233 mutex_lock(&hdmi->mutex);
234 hdmi->plugged_cb = fn;
235 hdmi->codec_dev = codec_dev;
236 plugged = hdmi->last_connector_result == connector_status_connected;
238 mutex_unlock(&hdmi->mutex);
246 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
287 if (!hdmi->unwedge_state)
290 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
324 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
326 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
333 struct dw_hdmi_i2c *i2c = hdmi->i2c;
336 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
340 return -EAGAIN;
343 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
345 return -EAGAIN;
349 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
350 return -EIO;
358 struct dw_hdmi_i2c *i2c = hdmi->i2c;
361 if (!i2c->is_regaddr) {
362 dev_dbg(hdmi->dev, "set read register address to 0\n");
363 i2c->slave_reg = 0x00;
364 i2c->is_regaddr = true;
367 while (length--) {
368 reinit_completion(&i2c->cmp);
370 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
371 if (i2c->is_segment)
384 i2c->is_segment = false;
392 struct dw_hdmi_i2c *i2c = hdmi->i2c;
395 if (!i2c->is_regaddr) {
397 i2c->slave_reg = buf[0];
398 length--;
400 i2c->is_regaddr = true;
403 while (length--) {
404 reinit_completion(&i2c->cmp);
407 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
423 struct dw_hdmi_i2c *i2c = hdmi->i2c;
429 * The internal I2C controller does not support the multi-byte
434 return -EOPNOTSUPP;
436 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
440 dev_dbg(hdmi->dev,
443 return -EOPNOTSUPP;
447 mutex_lock(&i2c->lock);
456 i2c->is_regaddr = false;
459 i2c->is_segment = false;
462 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
465 i2c->is_segment = true;
487 mutex_unlock(&i2c->lock);
508 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
510 return ERR_PTR(-ENOMEM);
512 mutex_init(&i2c->lock);
513 init_completion(&i2c->cmp);
515 adap = &i2c->adap;
516 adap->owner = THIS_MODULE;
517 adap->dev.parent = hdmi->dev;
518 adap->algo = &dw_hdmi_algorithm;
519 strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
524 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
525 devm_kfree(hdmi->dev, i2c);
529 hdmi->i2c = i2c;
531 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
659 * can be up to 20 bits in total, so we need 64-bit math. Also
668 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
676 spin_lock_irq(&hdmi->audio_lock);
677 hdmi->audio_n = n;
678 hdmi->audio_cts = cts;
679 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
680 spin_unlock_irq(&hdmi->audio_lock);
685 mutex_lock(&hdmi->audio_mutex);
686 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
687 mutex_unlock(&hdmi->audio_mutex);
692 mutex_lock(&hdmi->audio_mutex);
693 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
694 hdmi->sample_rate);
695 mutex_unlock(&hdmi->audio_mutex);
700 mutex_lock(&hdmi->audio_mutex);
701 hdmi->sample_width = width;
702 mutex_unlock(&hdmi->audio_mutex);
708 mutex_lock(&hdmi->audio_mutex);
709 hdmi->sample_non_pcm = non_pcm;
710 mutex_unlock(&hdmi->audio_mutex);
716 mutex_lock(&hdmi->audio_mutex);
717 hdmi->sample_rate = rate;
718 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
719 hdmi->sample_rate);
720 mutex_unlock(&hdmi->audio_mutex);
728 mutex_lock(&hdmi->audio_mutex);
729 hdmi->channels = cnt;
744 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
747 mutex_unlock(&hdmi->audio_mutex);
753 mutex_lock(&hdmi->audio_mutex);
757 mutex_unlock(&hdmi->audio_mutex);
764 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
766 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
767 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
772 if (!hdmi->curr_conn)
775 return hdmi->curr_conn->eld;
780 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
782 int ch_mask = BIT(hdmi->channels) - 1;
784 switch (hdmi->sample_rate) {
817 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
821 hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2);
836 if (hdmi->sample_rate == 192000 && hdmi->channels == 8 &&
837 hdmi->sample_width == 32 && hdmi->sample_non_pcm)
840 if (pdata->enable_audio)
841 pdata->enable_audio(hdmi,
842 hdmi->channels,
843 hdmi->sample_width,
844 hdmi->sample_rate,
845 hdmi->sample_non_pcm);
850 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
852 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
855 if (pdata->disable_audio)
856 pdata->disable_audio(hdmi);
863 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
868 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
873 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
886 spin_lock_irqsave(&hdmi->audio_lock, flags);
887 hdmi->audio_enable = true;
888 if (hdmi->enable_audio)
889 hdmi->enable_audio(hdmi);
890 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
898 spin_lock_irqsave(&hdmi->audio_lock, flags);
899 hdmi->audio_enable = false;
900 if (hdmi->disable_audio)
901 hdmi->disable_audio(hdmi);
902 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
1004 switch (hdmi->hdmi_data.enc_in_bus_format) {
1054 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
1069 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1072 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
1073 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
1076 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
1081 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1084 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
1085 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
1093 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
1096 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1097 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1117 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1118 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1121 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1126 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1132 hdmi->hdmi_data.rgb_limited_range) {
1166 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1202 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1207 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1208 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1209 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1211 hdmi->hdmi_data.enc_out_bus_format)) {
1229 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1231 hdmi->hdmi_data.enc_out_bus_format)) {
1255 ((hdmi_data->pix_repet_factor <<
1261 * Source shall only send GCPs with non-zero CD to sinks
1264 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
1277 if (hdmi_data->pix_repet_factor > 1) {
1323 /* -----------------------------------------------------------------------------
1339 if (msec-- == 0)
1368 if (hdmi->version < 0x200a)
1372 if (!hdmi->ddc)
1375 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1376 if (!display->hdmi.scdc.supported ||
1377 !display->hdmi.scdc.scrambling.supported)
1384 if (!display->hdmi.scdc.scrambling.low_rates &&
1385 display->max_tmds_clock <= 340000)
1393 * - The Source shall suspend transmission of the TMDS clock and data
1394 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1396 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1407 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1409 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1412 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 1);
1414 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 0);
1496 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1500 if (phy->gen == 1) {
1521 dev_warn(hdmi->dev, "PHY failed to power down\n");
1523 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1530 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1534 if (phy->gen == 1) {
1556 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1557 return -ETIMEDOUT;
1560 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1565 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1573 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1574 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1575 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1579 /* PLL/MPLL Cfg - always match on final entry */
1580 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1581 if (mpixelclock <= mpll_config->mpixelclock)
1584 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1585 if (mpixelclock <= curr_ctrl->mpixelclock)
1588 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1589 if (mpixelclock <= phy_config->mpixelclock)
1592 if (mpll_config->mpixelclock == ~0UL ||
1593 curr_ctrl->mpixelclock == ~0UL ||
1594 phy_config->mpixelclock == ~0UL)
1595 return -EINVAL;
1597 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1599 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1601 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1608 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1609 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1611 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1614 /* Override and disable clock termination. */
1624 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1625 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1626 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1627 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1635 if (phy->has_svsret)
1645 if (pdata->configure_phy)
1646 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1648 ret = phy->configure(hdmi, pdata, mpixelclock);
1650 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1697 u8 old_mask = hdmi->phy_mask;
1700 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1702 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1704 if (old_mask != hdmi->phy_mask)
1705 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1720 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1738 /* -----------------------------------------------------------------------------
1739 * HDMI TX Setup
1746 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1771 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1773 hdmi->hdmi_data.rgb_limited_range ?
1782 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1784 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1786 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1792 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1793 switch (hdmi->hdmi_data.enc_out_encoding) {
1795 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1803 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1860 /* AVI Data Byte 5- set up input and output pixel repetition */
1861 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1864 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1877 /* AVI Data Bytes 6-13 */
1909 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1945 const struct drm_connector_state *conn_state = connector->state;
1951 if (!hdmi->plat_data->use_drm_infoframe)
1963 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1983 const struct drm_hdmi_info *hdmi_info = &display->hdmi;
1984 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1988 vmode->mpixelclock = mode->clock * 1000;
1990 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1992 vmode->mtmdsclock = vmode->mpixelclock;
1994 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1996 hdmi->hdmi_data.enc_out_bus_format)) {
1998 vmode->mtmdsclock = vmode->mpixelclock * 2;
2001 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
2004 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
2009 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2010 vmode->mtmdsclock /= 2;
2012 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
2015 inv_val = (hdmi->hdmi_data.hdcp_enable ||
2017 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
2018 hdmi_info->scdc.scrambling.low_rates)) ?
2022 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
2026 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
2030 inv_val |= (vmode->mdataenablepolarity ?
2034 if (hdmi->vic == 39)
2037 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
2041 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
2045 inv_val |= hdmi->sink_is_hdmi ?
2051 hdisplay = mode->hdisplay;
2052 hblank = mode->htotal - mode->hdisplay;
2053 h_de_hs = mode->hsync_start - mode->hdisplay;
2054 hsync_len = mode->hsync_end - mode->hsync_start;
2060 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
2067 vdisplay = mode->vdisplay;
2068 vblank = mode->vtotal - mode->vdisplay;
2069 v_de_vs = mode->vsync_start - mode->vdisplay;
2070 vsync_len = mode->vsync_end - mode->vsync_start;
2076 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2085 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
2086 hdmi_info->scdc.scrambling.low_rates) {
2096 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
2098 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
2102 drm_scdc_set_scrambling(hdmi->curr_conn, 1);
2106 * that the quasi-static configuration bit
2118 drm_scdc_set_scrambling(hdmi->curr_conn, 0);
2166 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2171 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2172 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2174 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2175 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2179 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2180 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2185 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2186 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2206 * The number of iterations matters and depends on the HDMI TX revision
2215 switch (hdmi->version) {
2246 hdmi->vic = drm_match_cea_mode(mode);
2248 if (!hdmi->vic) {
2249 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2251 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2254 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2255 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2256 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2257 (hdmi->vic == 17) || (hdmi->vic == 18))
2258 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2260 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2262 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2263 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2265 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)
2266 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2269 if (hdmi->plat_data->input_bus_encoding)
2270 hdmi->hdmi_data.enc_in_encoding =
2271 hdmi->plat_data->input_bus_encoding;
2273 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2275 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)
2276 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2278 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
2282 hdmi->hdmi_data.pix_repet_factor = 0;
2283 hdmi->hdmi_data.hdcp_enable = 0;
2284 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2287 hdmi_av_composer(hdmi, &connector->display_info, mode);
2290 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2291 &connector->display_info,
2292 &hdmi->previous_mode);
2295 hdmi->phy.enabled = true;
2300 if (hdmi->sink_has_audio) {
2301 dev_dbg(hdmi->dev, "sink has audio support\n");
2303 /* HDMI Initialization Step E - Configure audio */
2305 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2309 if (hdmi->sink_is_hdmi) {
2310 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2312 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2317 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2383 hdmi->bridge_is_on = true;
2387 * is only be called when !hdmi->disabled.
2389 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2394 if (hdmi->phy.enabled) {
2395 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2396 hdmi->phy.enabled = false;
2399 hdmi->bridge_is_on = false;
2404 int force = hdmi->force;
2406 if (hdmi->disabled) {
2409 if (hdmi->rxsense)
2416 if (hdmi->bridge_is_on)
2419 if (!hdmi->bridge_is_on)
2438 if (hdmi->phy.ops->update_hpd)
2439 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2440 hdmi->force, hdmi->disabled,
2441 hdmi->rxsense);
2448 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2449 hdmi->last_connector_result = result;
2460 if (!hdmi->ddc)
2463 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
2465 dev_dbg(hdmi->dev, "failed to get edid\n");
2470 * FIXME: This should use connector->display_info.is_hdmi and
2471 * connector->display_info.has_audio from a path that has read the EDID
2476 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2477 edid->width_cm, edid->height_cm);
2479 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2480 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2485 /* -----------------------------------------------------------------------------
2507 cec_notifier_set_phys_addr(hdmi->cec_notifier,
2508 connector->display_info.source_physical_address);
2522 struct drm_crtc *crtc = new_state->crtc;
2533 crtc_state->mode_changed = true;
2544 mutex_lock(&hdmi->mutex);
2545 hdmi->force = connector->force;
2548 mutex_unlock(&hdmi->mutex);
2568 struct drm_connector *connector = &hdmi->connector;
2572 if (hdmi->version >= 0x200a)
2573 connector->ycbcr_420_allowed =
2574 hdmi->plat_data->ycbcr_420_allowed;
2576 connector->ycbcr_420_allowed = false;
2578 connector->interlace_allowed = 1;
2579 connector->polled = DRM_CONNECTOR_POLL_HPD;
2583 drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
2586 hdmi->ddc);
2596 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
2599 drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
2603 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2605 return -ENOMEM;
2607 mutex_lock(&hdmi->cec_notifier_mutex);
2608 hdmi->cec_notifier = notifier;
2609 mutex_unlock(&hdmi->cec_notifier_mutex);
2614 /* -----------------------------------------------------------------------------
2620 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
2621 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
2622 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
2623 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
2624 * - MEDIA_BUS_FMT_RGB888_1X24,
2625 * - MEDIA_BUS_FMT_YUV16_1X48,
2626 * - MEDIA_BUS_FMT_RGB161616_1X48,
2627 * - MEDIA_BUS_FMT_UYVY12_1X24,
2628 * - MEDIA_BUS_FMT_YUV12_1X36,
2629 * - MEDIA_BUS_FMT_RGB121212_1X36,
2630 * - MEDIA_BUS_FMT_UYVY10_1X20,
2631 * - MEDIA_BUS_FMT_YUV10_1X30,
2632 * - MEDIA_BUS_FMT_RGB101010_1X30,
2633 * - MEDIA_BUS_FMT_UYVY8_1X16,
2634 * - MEDIA_BUS_FMT_YUV8_1X24,
2646 struct drm_connector *conn = conn_state->connector;
2647 struct drm_display_info *info = &conn->display_info;
2648 struct drm_display_mode *mode = &crtc_state->mode;
2649 u8 max_bpc = conn_state->max_requested_bpc;
2650 bool is_hdmi2_sink = info->hdmi.scdc.supported ||
2651 (info->color_formats & DRM_COLOR_FORMAT_YCBCR420);
2662 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
2663 if (list_is_singular(&bridge->encoder->bridge_chain) ||
2664 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
2675 if (conn->ycbcr_420_allowed &&
2680 if (max_bpc >= 16 && info->bpc == 16 &&
2681 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
2684 if (max_bpc >= 12 && info->bpc >= 12 &&
2685 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
2688 if (max_bpc >= 10 && info->bpc >= 10 &&
2689 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
2709 if (max_bpc >= 16 && info->bpc == 16) {
2710 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2716 if (max_bpc >= 12 && info->bpc >= 12) {
2717 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2720 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2726 if (max_bpc >= 10 && info->bpc >= 10) {
2727 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2730 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2736 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2739 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2749 * - MEDIA_BUS_FMT_RGB888_1X24
2750 * - MEDIA_BUS_FMT_YUV8_1X24
2751 * - MEDIA_BUS_FMT_UYVY8_1X16
2752 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
2753 * - MEDIA_BUS_FMT_RGB101010_1X30
2754 * - MEDIA_BUS_FMT_YUV10_1X30
2755 * - MEDIA_BUS_FMT_UYVY10_1X20
2756 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
2757 * - MEDIA_BUS_FMT_RGB121212_1X36
2758 * - MEDIA_BUS_FMT_YUV12_1X36
2759 * - MEDIA_BUS_FMT_UYVY12_1X24
2760 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
2761 * - MEDIA_BUS_FMT_RGB161616_1X48
2762 * - MEDIA_BUS_FMT_YUV16_1X48
2763 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
2876 struct dw_hdmi *hdmi = bridge->driver_private;
2878 hdmi->hdmi_data.enc_out_bus_format =
2879 bridge_state->output_bus_cfg.format;
2881 hdmi->hdmi_data.enc_in_bus_format =
2882 bridge_state->input_bus_cfg.format;
2884 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
2885 bridge_state->input_bus_cfg.format,
2886 bridge_state->output_bus_cfg.format);
2895 struct dw_hdmi *hdmi = bridge->driver_private;
2898 return drm_bridge_attach(encoder, hdmi->next_bridge,
2906 struct dw_hdmi *hdmi = bridge->driver_private;
2908 mutex_lock(&hdmi->cec_notifier_mutex);
2909 cec_notifier_conn_unregister(hdmi->cec_notifier);
2910 hdmi->cec_notifier = NULL;
2911 mutex_unlock(&hdmi->cec_notifier_mutex);
2919 struct dw_hdmi *hdmi = bridge->driver_private;
2920 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
2923 /* We don't support double-clocked modes */
2924 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2927 if (pdata->mode_valid)
2928 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
2938 struct dw_hdmi *hdmi = bridge->driver_private;
2940 mutex_lock(&hdmi->mutex);
2943 drm_mode_copy(&hdmi->previous_mode, mode);
2945 mutex_unlock(&hdmi->mutex);
2951 struct dw_hdmi *hdmi = bridge->driver_private;
2953 mutex_lock(&hdmi->mutex);
2954 hdmi->disabled = true;
2955 hdmi->curr_conn = NULL;
2959 mutex_unlock(&hdmi->mutex);
2965 struct dw_hdmi *hdmi = bridge->driver_private;
2969 bridge->encoder);
2971 mutex_lock(&hdmi->mutex);
2972 hdmi->disabled = false;
2973 hdmi->curr_conn = connector;
2977 mutex_unlock(&hdmi->mutex);
2982 struct dw_hdmi *hdmi = bridge->driver_private;
2990 struct dw_hdmi *hdmi = bridge->driver_private;
3012 /* -----------------------------------------------------------------------------
3018 struct dw_hdmi_i2c *i2c = hdmi->i2c;
3027 i2c->stat = stat;
3029 complete(&i2c->cmp);
3040 if (hdmi->i2c)
3054 mutex_lock(&hdmi->mutex);
3056 if (!hdmi->force) {
3062 hdmi->rxsense = false;
3071 hdmi->rxsense = true;
3076 mutex_unlock(&hdmi->mutex);
3107 * load - in other words, there's something listening on the
3110 * ask the source to re-read the EDID.
3119 mutex_lock(&hdmi->cec_notifier_mutex);
3120 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
3121 mutex_unlock(&hdmi->cec_notifier_mutex);
3132 dev_dbg(hdmi->dev, "EVENT=%s\n",
3136 if (hdmi->bridge.dev) {
3137 drm_helper_hpd_irq_event(hdmi->bridge.dev);
3138 drm_bridge_hpd_notify(&hdmi->bridge, status);
3152 .name = "DWC HDMI TX PHY",
3168 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
3173 .name = "DWC HDMI 3D TX PHY",
3178 .name = "DWC HDMI 2.0 TX PHY",
3193 phy_type = hdmi->plat_data->phy_force_vendor ?
3199 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
3200 dev_err(hdmi->dev,
3202 return -ENODEV;
3205 hdmi->phy.ops = hdmi->plat_data->phy_ops;
3206 hdmi->phy.data = hdmi->plat_data->phy_data;
3207 hdmi->phy.name = hdmi->plat_data->phy_name;
3214 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
3215 hdmi->phy.name = dw_hdmi_phys[i].name;
3216 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
3219 !hdmi->plat_data->configure_phy) {
3220 dev_err(hdmi->dev, "%s requires platform support\n",
3221 hdmi->phy.name);
3222 return -ENODEV;
3229 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
3230 return -ENODEV;
3235 mutex_lock(&hdmi->mutex);
3236 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
3237 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3238 mutex_unlock(&hdmi->mutex);
3243 mutex_lock(&hdmi->mutex);
3244 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
3245 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3246 mutex_unlock(&hdmi->mutex);
3281 if (hdmi->phy.ops->setup_hpd)
3282 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
3285 /* -----------------------------------------------------------------------------
3293 if (!hdmi->plat_data->output_port)
3297 remote = of_graph_get_remote_node(hdmi->dev->of_node,
3298 hdmi->plat_data->output_port,
3299 -1);
3301 return -ENODEV;
3303 hdmi->next_bridge = of_drm_find_bridge(remote);
3305 if (!hdmi->next_bridge)
3306 return -EPROBE_DEFER;
3313 return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format);
3320 struct device *dev = &pdev->dev;
3321 struct device_node *np = dev->of_node;
3340 hdmi->plat_data = plat_data;
3341 hdmi->dev = dev;
3342 hdmi->sample_rate = 48000;
3343 hdmi->channels = 2;
3344 hdmi->disabled = true;
3345 hdmi->rxsense = true;
3346 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
3347 hdmi->mc_clkdis = 0x7f;
3348 hdmi->last_connector_result = connector_status_disconnected;
3350 mutex_init(&hdmi->mutex);
3351 mutex_init(&hdmi->audio_mutex);
3352 mutex_init(&hdmi->cec_notifier_mutex);
3353 spin_lock_init(&hdmi->audio_lock);
3359 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
3361 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
3363 if (!hdmi->ddc) {
3364 dev_dbg(hdmi->dev, "failed to read ddc node\n");
3365 return ERR_PTR(-EPROBE_DEFER);
3369 dev_dbg(hdmi->dev, "no ddc property found\n");
3372 if (!plat_data->regm) {
3375 of_property_read_u32(np, "reg-io-width", &val);
3379 hdmi->reg_shift = 2;
3385 dev_err(dev, "reg-io-width must be 1 or 4\n");
3386 return ERR_PTR(-EINVAL);
3390 hdmi->regs = devm_ioremap_resource(dev, iores);
3391 if (IS_ERR(hdmi->regs)) {
3392 ret = PTR_ERR(hdmi->regs);
3396 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
3397 if (IS_ERR(hdmi->regm)) {
3399 ret = PTR_ERR(hdmi->regm);
3403 hdmi->regm = plat_data->regm;
3406 clk = devm_clk_get_enabled(hdmi->dev, "isfr");
3409 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
3413 clk = devm_clk_get_enabled(hdmi->dev, "iahb");
3416 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3420 clk = devm_clk_get_optional_enabled(hdmi->dev, "cec");
3423 if (ret != -EPROBE_DEFER)
3424 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
3430 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
3438 hdmi->version, prod_id0, prod_id1);
3439 ret = -ENODEV;
3447 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3448 hdmi->version >> 12, hdmi->version & 0xfff,
3450 hdmi->phy.name);
3473 if (!hdmi->ddc) {
3475 hdmi->pinctrl = devm_pinctrl_get(dev);
3476 if (!IS_ERR(hdmi->pinctrl)) {
3477 hdmi->unwedge_state =
3478 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
3479 hdmi->default_state =
3480 pinctrl_lookup_state(hdmi->pinctrl, "default");
3482 if (IS_ERR(hdmi->default_state) ||
3483 IS_ERR(hdmi->unwedge_state)) {
3484 if (!IS_ERR(hdmi->unwedge_state))
3487 hdmi->default_state = NULL;
3488 hdmi->unwedge_state = NULL;
3492 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
3493 if (IS_ERR(hdmi->ddc))
3494 hdmi->ddc = NULL;
3497 hdmi->bridge.driver_private = hdmi;
3498 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
3500 hdmi->bridge.interlace_allowed = true;
3501 hdmi->bridge.ddc = hdmi->ddc;
3502 hdmi->bridge.of_node = pdev->dev.of_node;
3503 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
3505 if (hdmi->version >= 0x200a)
3506 hdmi->bridge.ycbcr_420_allowed = plat_data->ycbcr_420_allowed;
3518 audio.phys = iores->start;
3519 audio.base = hdmi->regs;
3523 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
3524 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
3526 pdevinfo.name = "dw-hdmi-ahb-audio";
3530 hdmi->audio = platform_device_register_full(&pdevinfo);
3538 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
3539 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
3541 pdevinfo.name = "dw-hdmi-i2s-audio";
3545 hdmi->audio = platform_device_register_full(&pdevinfo);
3549 audio.phys = iores->start;
3550 audio.base = hdmi->regs;
3555 hdmi->enable_audio = dw_hdmi_gp_audio_enable;
3556 hdmi->disable_audio = dw_hdmi_gp_audio_disable;
3558 pdevinfo.name = "dw-hdmi-gp-audio";
3563 hdmi->audio = platform_device_register_full(&pdevinfo);
3566 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
3571 pdevinfo.name = "dw-hdmi-cec";
3576 hdmi->cec = platform_device_register_full(&pdevinfo);
3579 drm_bridge_add(&hdmi->bridge);
3584 i2c_put_adapter(hdmi->ddc);
3592 drm_bridge_remove(&hdmi->bridge);
3594 if (hdmi->audio && !IS_ERR(hdmi->audio))
3595 platform_device_unregister(hdmi->audio);
3596 if (!IS_ERR(hdmi->cec))
3597 platform_device_unregister(hdmi->cec);
3602 if (hdmi->i2c)
3603 i2c_del_adapter(&hdmi->i2c->adap);
3605 i2c_put_adapter(hdmi->ddc);
3609 /* -----------------------------------------------------------------------------
3623 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
3646 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3647 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3651 MODULE_ALIAS("platform:dw-hdmi");