Lines Matching +full:esc +full:- +full:clock +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/media-bus-format.h>
25 #include <drm/bridge/samsung-dsim.h>
112 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
113 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
243 DSIM_CLKCTRL_REG, /* Clock control register */
501 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
536 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
541 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
546 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
549 dev_err(dsi->dev, "timeout waiting for reset\n");
554 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
556 reinit_completion(&dsi->completed);
569 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
577 p_min = DIV_ROUND_UP(fin, (driver_data->pll_fin_max * MHZ));
578 p_max = fin / (driver_data->pll_fin_min * MHZ);
588 if (_m < driver_data->m_min || _m > driver_data->m_max)
593 if (tmp < driver_data->min_freq * MHZ ||
594 tmp > driver_data->max_freq * MHZ)
600 delta = abs(fout - tmp);
623 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
630 if (dsi->pll_clk) {
632 * Ensure that the reference clock is generated with a power of
636 fin = clk_get_rate(clk_get_parent(dsi->pll_clk));
637 while (fin > driver_data->pll_fin_max * MHZ)
639 clk_set_rate(dsi->pll_clk, fin);
641 fin = clk_get_rate(dsi->pll_clk);
643 fin = dsi->pll_clk_rate;
645 dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin);
649 dev_err(dsi->dev,
650 "failed to find PLL PMS for requested frequency\n");
653 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
655 writel(driver_data->reg_values[PLL_TIMER],
656 dsi->reg_base + driver_data->plltmr_reg);
658 reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
661 if (driver_data->has_freqband) {
674 dev_dbg(dsi->dev, "band %d\n", band);
679 if (dsi->swap_dn_dp_clk)
681 if (dsi->swap_dn_dp_data)
688 if (timeout-- == 0) {
689 dev_err(dsi->dev, "PLL failed to stabilize\n");
695 dsi->hs_clock = fout;
705 struct drm_display_mode *m = &dsi->mode;
706 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
708 /* m->clock is in KHz */
709 pix_clk = m->clock * 1000;
712 if (dsi->burst_clk_rate)
713 hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
715 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes));
718 dev_err(dsi->dev, "failed to configure DSI PLL\n");
719 return -EFAULT;
723 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
731 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
741 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
751 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
752 const unsigned int *reg_values = driver_data->reg_values;
757 unsigned long long byte_clock = dsi->hs_clock / 8;
759 if (driver_data->has_freqband)
762 phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock,
763 dsi->lanes, &cfg);
791 /* B D-PHY: D-PHY Master & Slave Analog Block control */
798 * T LPX: Transmitted length of any Low-Power state period
799 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
808 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
809 * Line state immediately before the HS-0 Line state starting the
811 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
812 * transmitting the Clock.
813 * T CLK_POST: Time that the transmitter continues to send HS clock
815 * Interval is defined as the period from the end of T HS-TRAIL to
816 * the beginning of T CLK-TRAIL
817 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
818 * the last payload clock bit of a HS transmission burst
829 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
830 * Line state immediately before the HS-0 Line state starting the
832 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
834 * T HS-TRAIL: Time that the transmitter drives the flipped differential
863 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
870 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
894 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
901 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
903 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
905 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
907 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
909 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
911 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
913 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
915 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
919 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
922 switch (dsi->format) {
936 dev_err(dsi->dev, "invalid pixel format\n");
937 return -EINVAL;
941 * Use non-continuous clock mode if the periparal wants and
944 * In non-continous clock mode, host controller will turn off
945 * the HS clock between high-speed transmissions to reduce
948 if (driver_data->has_clklane_stop &&
949 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
950 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type))
957 lanes_mask = BIT(dsi->lanes) - 1;
960 /* Check clock and data lane state are stop state */
963 if (timeout-- == 0) {
964 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
965 return -EFAULT;
976 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
987 struct drm_display_mode *m = &dsi->mode;
988 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
991 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
992 u64 byte_clk = dsi->hs_clock / 8;
993 u64 pix_clk = m->clock * 1000;
995 int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk);
996 int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk);
997 int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk);
1000 hfp = max(hfp - 6, 0);
1001 hbp = max(hbp - 6, 0);
1002 hsa = max(hsa - 6, 0);
1004 dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u",
1008 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
1009 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
1015 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
1019 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
1020 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
1024 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
1046 if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) {
1063 } while (--timeout);
1065 return -ETIMEDOUT;
1091 struct device *dev = dsi->dev;
1092 struct mipi_dsi_packet *pkt = &xfer->packet;
1093 const u8 *payload = pkt->payload + xfer->tx_done;
1094 u16 length = pkt->payload_length - xfer->tx_done;
1095 bool first = !xfer->tx_done;
1099 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1104 xfer->tx_done += length;
1111 length -= 4;
1132 reg = get_unaligned_le32(pkt->header);
1138 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1139 dsi->state & DSIM_STATE_CMD_LPM)) {
1140 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1141 dsi->state ^= DSIM_STATE_CMD_LPM;
1146 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1153 u8 *payload = xfer->rx_payload + xfer->rx_done;
1154 bool first = !xfer->rx_done;
1155 struct device *dev = dsi->dev;
1165 if (xfer->rx_len >= 2) {
1167 ++xfer->rx_done;
1173 ++xfer->rx_done;
1174 xfer->rx_len = xfer->rx_done;
1175 xfer->result = 0;
1179 xfer->result = 0;
1184 if (length > xfer->rx_len) {
1187 xfer->rx_len, length);
1188 length = xfer->rx_len;
1189 } else if (length < xfer->rx_len) {
1190 xfer->rx_len = length;
1194 length = xfer->rx_len - xfer->rx_done;
1195 xfer->rx_done += length;
1205 length -= 4;
1222 if (xfer->rx_done == xfer->rx_len)
1223 xfer->result = 0;
1231 } while (--length);
1241 spin_lock_irqsave(&dsi->transfer_lock, flags);
1243 if (list_empty(&dsi->transfer_list)) {
1244 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1248 xfer = list_first_entry(&dsi->transfer_list,
1251 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1253 if (xfer->packet.payload_length &&
1254 xfer->tx_done == xfer->packet.payload_length)
1260 if (xfer->packet.payload_length || xfer->rx_len)
1263 xfer->result = 0;
1264 complete(&xfer->completed);
1266 spin_lock_irqsave(&dsi->transfer_lock, flags);
1268 list_del_init(&xfer->list);
1269 start = !list_empty(&dsi->transfer_list);
1271 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1283 spin_lock_irqsave(&dsi->transfer_lock, flags);
1285 if (list_empty(&dsi->transfer_list)) {
1286 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1290 xfer = list_first_entry(&dsi->transfer_list,
1293 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1295 dev_dbg(dsi->dev,
1297 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1298 xfer->rx_done);
1300 if (xfer->tx_done != xfer->packet.payload_length)
1303 if (xfer->rx_done != xfer->rx_len)
1306 if (xfer->rx_done != xfer->rx_len)
1309 spin_lock_irqsave(&dsi->transfer_lock, flags);
1311 list_del_init(&xfer->list);
1312 start = !list_empty(&dsi->transfer_list);
1314 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1316 if (!xfer->rx_len)
1317 xfer->result = 0;
1318 complete(&xfer->completed);
1329 spin_lock_irqsave(&dsi->transfer_lock, flags);
1331 if (!list_empty(&dsi->transfer_list) &&
1332 xfer == list_first_entry(&dsi->transfer_list,
1334 list_del_init(&xfer->list);
1335 start = !list_empty(&dsi->transfer_list);
1336 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1342 list_del_init(&xfer->list);
1344 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1353 xfer->tx_done = 0;
1354 xfer->rx_done = 0;
1355 xfer->result = -ETIMEDOUT;
1356 init_completion(&xfer->completed);
1358 spin_lock_irqsave(&dsi->transfer_lock, flags);
1360 stopped = list_empty(&dsi->transfer_list);
1361 list_add_tail(&xfer->list, &dsi->transfer_list);
1363 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1368 wait_for_completion_timeout(&xfer->completed,
1370 if (xfer->result == -ETIMEDOUT) {
1371 struct mipi_dsi_packet *pkt = &xfer->packet;
1374 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1375 (int)pkt->payload_length, pkt->payload);
1376 return -ETIMEDOUT;
1380 return xfer->result;
1393 dev_warn(dsi->dev, "spurious interrupt\n");
1405 complete(&dsi->completed);
1421 enable_irq(dsi->irq);
1423 if (dsi->te_gpio)
1424 enable_irq(gpiod_to_irq(dsi->te_gpio));
1429 if (dsi->te_gpio)
1430 disable_irq(gpiod_to_irq(dsi->te_gpio));
1432 disable_irq(dsi->irq);
1437 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1439 if (dsi->state & DSIM_STATE_INITIALIZED)
1445 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1446 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);
1449 if (driver_data->wait_for_reset)
1454 dsi->state |= DSIM_STATE_INITIALIZED;
1465 if (dsi->state & DSIM_STATE_ENABLED)
1468 ret = pm_runtime_resume_and_get(dsi->dev);
1470 dev_err(dsi->dev, "failed to enable DSI device.\n");
1474 dsi->state |= DSIM_STATE_ENABLED;
1477 * For Exynos-DSIM the downstream bridge, or panel are expecting
1480 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1495 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1503 if (!(dsi->state & DSIM_STATE_ENABLED))
1507 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1515 dsi->state &= ~DSIM_STATE_ENABLED;
1516 pm_runtime_put_sync(dsi->dev);
1521 * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
1585 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1601 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) {
1602 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1603 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1604 } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) {
1605 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1606 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1619 if (dsi->lanes > 1) {
1620 int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
1621 int remainder = hfp % dsi->lanes;
1624 adjusted_mode->hsync_start += remainder;
1625 adjusted_mode->hsync_end += remainder;
1626 adjusted_mode->htotal += remainder;
1639 drm_mode_copy(&dsi->mode, adjusted_mode);
1647 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge,
1668 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1670 if (pdata->host_ops && pdata->host_ops->te_irq_handler)
1671 return pdata->host_ops->te_irq_handler(dsi);
1681 dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN);
1682 if (!dsi->te_gpio)
1684 else if (IS_ERR(dsi->te_gpio))
1685 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n");
1687 te_gpio_irq = gpiod_to_irq(dsi->te_gpio);
1692 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1693 gpiod_put(dsi->te_gpio);
1704 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1705 struct device *dev = dsi->dev;
1706 struct device_node *np = dev->of_node;
1713 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
1730 * device-tree node.
1733 return -ENODEV;
1739 return -ENODEV;
1743 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel);
1745 dsi->out_bridge = of_drm_find_bridge(remote);
1746 if (!dsi->out_bridge)
1747 dsi->out_bridge = ERR_PTR(-EINVAL);
1752 if (IS_ERR(dsi->out_bridge)) {
1753 ret = PTR_ERR(dsi->out_bridge);
1758 DRM_DEV_INFO(dev, "Attached %s device (lanes:%d bpp:%d mode-flags:0x%lx)\n",
1759 device->name, device->lanes,
1760 mipi_dsi_pixel_format_to_bpp(device->format),
1761 device->mode_flags);
1763 drm_bridge_add(&dsi->bridge);
1771 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1772 ret = samsung_dsim_register_te_irq(dsi, &device->dev);
1777 if (pdata->host_ops && pdata->host_ops->attach) {
1778 ret = pdata->host_ops->attach(dsi, device);
1783 dsi->lanes = device->lanes;
1784 dsi->format = device->format;
1785 dsi->mode_flags = device->mode_flags;
1792 if (dsi->te_gpio) {
1793 free_irq(gpiod_to_irq(dsi->te_gpio), dsi);
1794 gpiod_put(dsi->te_gpio);
1802 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1804 dsi->out_bridge = NULL;
1806 if (pdata->host_ops && pdata->host_ops->detach)
1807 pdata->host_ops->detach(dsi, device);
1811 drm_bridge_remove(&dsi->bridge);
1823 if (!(dsi->state & DSIM_STATE_ENABLED))
1824 return -EINVAL;
1834 xfer.rx_len = msg->rx_len;
1835 xfer.rx_payload = msg->rx_buf;
1836 xfer.flags = msg->flags;
1861 struct device *dev = dsi->dev;
1862 struct device_node *node = dev->of_node;
1867 ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
1868 &dsi->pll_clk_rate, 1);
1869 /* If it doesn't exist, read it from the clock instead of failing */
1871 dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n");
1872 dsi->pll_clk = devm_clk_get(dev, "sclk_mipi");
1873 if (IS_ERR(dsi->pll_clk))
1874 return PTR_ERR(dsi->pll_clk);
1877 /* If it doesn't exist, use pixel clock instead of failing */
1878 ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
1879 &dsi->burst_clk_rate, 1);
1881 dev_dbg(dev, "Using pixel clock for HS clock frequency\n");
1882 dsi->burst_clk_rate = 0;
1885 ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
1886 &dsi->esc_clk_rate, 0);
1890 endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
1891 nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1893 /* Polarity 0 is clock lane, 1..4 are data lanes. */
1894 of_property_read_u32_array(endpoint, "lane-polarities",
1898 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
1901 dsi->swap_dn_dp_clk = true;
1903 dsi->swap_dn_dp_data = true;
1911 return mipi_dsi_host_register(&dsi->dsi_host);
1916 mipi_dsi_host_unregister(&dsi->dsi_host);
1934 struct device *dev = &pdev->dev;
1940 return -ENOMEM;
1942 init_completion(&dsi->completed);
1943 spin_lock_init(&dsi->transfer_lock);
1944 INIT_LIST_HEAD(&dsi->transfer_list);
1946 dsi->dsi_host.ops = &samsung_dsim_ops;
1947 dsi->dsi_host.dev = dev;
1949 dsi->dev = dev;
1950 dsi->plat_data = of_device_get_match_data(dev);
1951 dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type];
1953 dsi->supplies[0].supply = "vddcore";
1954 dsi->supplies[1].supply = "vddio";
1955 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1956 dsi->supplies);
1960 dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks,
1961 sizeof(*dsi->clks), GFP_KERNEL);
1962 if (!dsi->clks)
1963 return -ENOMEM;
1965 for (i = 0; i < dsi->driver_data->num_clks; i++) {
1966 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1967 if (IS_ERR(dsi->clks[i])) {
1969 dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
1970 if (!IS_ERR(dsi->clks[i]))
1974 dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
1975 return PTR_ERR(dsi->clks[i]);
1979 dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
1980 if (IS_ERR(dsi->reg_base))
1981 return PTR_ERR(dsi->reg_base);
1983 dsi->phy = devm_phy_optional_get(dev, "dsim");
1984 if (IS_ERR(dsi->phy)) {
1986 return PTR_ERR(dsi->phy);
1989 dsi->irq = platform_get_irq(pdev, 0);
1990 if (dsi->irq < 0)
1991 return dsi->irq;
1993 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
2010 dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
2011 dsi->bridge.of_node = dev->of_node;
2012 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
2014 /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */
2015 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM)
2016 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low;
2018 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high;
2020 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host) {
2021 ret = dsi->plat_data->host_ops->register_host(dsi);
2039 pm_runtime_disable(&pdev->dev);
2041 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host)
2042 dsi->plat_data->host_ops->unregister_host(dsi);
2049 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2054 if (dsi->state & DSIM_STATE_INITIALIZED) {
2055 dsi->state &= ~DSIM_STATE_INITIALIZED;
2062 dsi->state &= ~DSIM_STATE_CMD_LPM;
2064 phy_power_off(dsi->phy);
2066 for (i = driver_data->num_clks - 1; i > -1; i--)
2067 clk_disable_unprepare(dsi->clks[i]);
2069 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2071 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
2079 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2082 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2084 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
2088 for (i = 0; i < driver_data->num_clks; i++) {
2089 ret = clk_prepare_enable(dsi->clks[i]);
2094 ret = phy_power_on(dsi->phy);
2096 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
2103 while (--i > -1)
2104 clk_disable_unprepare(dsi->clks[i]);
2105 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2129 .compatible = "fsl,imx8mm-mipi-dsim",
2133 .compatible = "fsl,imx8mp-mipi-dsim",
2144 .name = "samsung-dsim",