Lines Matching +full:0 +full:x8006
32 #define KEY_DDC_ACCS_DONE 0x02
33 #define DDC_NO_ACK 0x50
35 #define LT9611_4LANES 0
66 #define LT9611_PAGE_CONTROL 0xff
71 .range_min = 0,
72 .range_max = 0x85ff,
74 .selector_mask = 0xff,
75 .selector_shift = 0,
76 .window_start = 0,
77 .window_len = 0x100,
84 .max_register = 0xffff,
97 { 0x8106, 0x40 }, /* port A rx current */
98 { 0x810a, 0xfe }, /* port A ldo voltage set */
99 { 0x810b, 0xbf }, /* enable port A lprx */
100 { 0x8111, 0x40 }, /* port B rx current */
101 { 0x8115, 0xfe }, /* port B ldo voltage set */
102 { 0x8116, 0xbf }, /* enable port B lprx */
104 { 0x811c, 0x03 }, /* PortA clk lane no-LP mode */
105 { 0x8120, 0x03 }, /* PortB clk lane with-LP mode */
115 { 0x8300, LT9611_4LANES },
116 { 0x830a, 0x00 },
117 { 0x824f, 0x80 },
118 { 0x8250, 0x10 },
119 { 0x8302, 0x0a },
120 { 0x8306, 0x0a },
124 reg_cfg[1].def = 0x03;
148 regmap_write(lt9611->regmap, 0x830d, (u8)(v_total / 256));
149 regmap_write(lt9611->regmap, 0x830e, (u8)(v_total % 256));
151 regmap_write(lt9611->regmap, 0x830f, (u8)(vactive / 256));
152 regmap_write(lt9611->regmap, 0x8310, (u8)(vactive % 256));
154 regmap_write(lt9611->regmap, 0x8311, (u8)(h_total / 256));
155 regmap_write(lt9611->regmap, 0x8312, (u8)(h_total % 256));
157 regmap_write(lt9611->regmap, 0x8313, (u8)(hactive / 256));
158 regmap_write(lt9611->regmap, 0x8314, (u8)(hactive % 256));
160 regmap_write(lt9611->regmap, 0x8315, (u8)(vsync_len % 256));
161 regmap_write(lt9611->regmap, 0x8316, (u8)(hsync_len % 256));
163 regmap_write(lt9611->regmap, 0x8317, (u8)(vfront_porch % 256));
165 regmap_write(lt9611->regmap, 0x8318, (u8)(vsync_porch % 256));
167 regmap_write(lt9611->regmap, 0x8319, (u8)(hfront_porch % 256));
169 regmap_write(lt9611->regmap, 0x831a, (u8)(hsync_porch / 256) |
171 regmap_write(lt9611->regmap, 0x831b, (u8)(hsync_porch % 256));
178 { 0x830b, 0x01 },
179 { 0x830c, 0x10 },
180 { 0x8348, 0x00 },
181 { 0x8349, 0x81 },
184 { 0x8321, 0x4a },
185 { 0x8324, 0x71 },
186 { 0x8325, 0x30 },
187 { 0x832a, 0x01 },
190 { 0x834a, 0x40 },
193 { 0x832d, 0x38 },
194 { 0x8331, 0x08 },
196 u8 pol = 0x10;
199 pol |= 0x2;
201 pol |= 0x1;
202 regmap_write(lt9611->regmap, 0x831d, pol);
209 hact += 0x50;
210 hact = min(hact, 0x3e0U);
211 regmap_write(lt9611->regmap, 0x830b, hact / 256);
212 regmap_write(lt9611->regmap, 0x830c, hact % 256);
213 regmap_write(lt9611->regmap, 0x8348, hact / 256);
214 regmap_write(lt9611->regmap, 0x8349, hact % 256);
217 regmap_write(lt9611->regmap, 0x8326, pcr_m);
220 regmap_write(lt9611->regmap, 0x8011, 0x5a);
221 regmap_write(lt9611->regmap, 0x8011, 0xfa);
229 { 0x8123, 0x40 },
230 { 0x8124, 0x64 },
231 { 0x8125, 0x80 },
232 { 0x8126, 0x55 },
233 { 0x812c, 0x37 },
234 { 0x812f, 0x01 },
235 { 0x8126, 0x55 },
236 { 0x8127, 0x66 },
237 { 0x8128, 0x88 },
238 { 0x812a, 0x20 },
244 regmap_write(lt9611->regmap, 0x812d, 0x88);
247 regmap_write(lt9611->regmap, 0x812d, 0x99);
250 regmap_write(lt9611->regmap, 0x812d, 0xaa);
258 * - write remainder to 7:0 bits, which means shift by 1
260 regmap_write(lt9611->regmap, 0x82e3, pclk >> 17); /* pclk[19:16] */
261 regmap_write(lt9611->regmap, 0x82e4, pclk >> 9); /* pclk[15:8] */
262 regmap_write(lt9611->regmap, 0x82e5, pclk >> 1); /* pclk[7:0] */
264 regmap_write(lt9611->regmap, 0x82de, 0x20);
265 regmap_write(lt9611->regmap, 0x82de, 0xe0);
267 regmap_write(lt9611->regmap, 0x8016, 0xf1);
268 regmap_write(lt9611->regmap, 0x8016, 0xf3);
270 return 0;
297 temp = lt9611_read_video_check(lt9611, 0x8282);
298 if (temp < 0)
303 temp = lt9611_read_video_check(lt9611, 0x826c);
304 if (temp < 0)
309 temp = lt9611_read_video_check(lt9611, 0x8286);
310 if (temp < 0)
315 temp = lt9611_read_video_check(lt9611, 0x8382);
316 if (temp < 0)
321 temp = lt9611_read_video_check(lt9611, 0x8386);
322 if (temp < 0)
330 return 0;
340 regmap_write(lt9611->regmap, 0x82d6, 0x8c);
342 regmap_write(lt9611->regmap, 0x82d6, 0x0c);
343 regmap_write(lt9611->regmap, 0x82d7, 0x04);
349 { 0x8130, 0x6a },
350 { 0x8131, 0x44 }, /* HDMI DC mode */
351 { 0x8132, 0x4a },
352 { 0x8133, 0x0b },
353 { 0x8134, 0x00 },
354 { 0x8135, 0x00 },
355 { 0x8136, 0x00 },
356 { 0x8137, 0x44 },
357 { 0x813f, 0x0f },
358 { 0x8140, 0xa0 },
359 { 0x8141, 0xa0 },
360 { 0x8142, 0xa0 },
361 { 0x8143, 0xa0 },
362 { 0x8144, 0x0a },
367 reg_cfg[2].def = 0x73;
375 unsigned int irq_flag0 = 0;
376 unsigned int irq_flag3 = 0;
378 regmap_read(lt9611->regmap, 0x820f, &irq_flag3);
379 regmap_read(lt9611->regmap, 0x820c, &irq_flag0);
382 if (irq_flag3 & 0x80) {
385 regmap_write(lt9611->regmap, 0x8207, 0xbf);
386 regmap_write(lt9611->regmap, 0x8207, 0x3f);
390 if (irq_flag3 & 0x40) {
393 regmap_write(lt9611->regmap, 0x8207, 0x7f);
394 regmap_write(lt9611->regmap, 0x8207, 0x3f);
397 if (irq_flag3 & 0xc0 && lt9611->bridge.dev)
401 if (irq_flag0 & 0x01) {
403 regmap_write(lt9611->regmap, 0x829e, 0xff);
404 regmap_write(lt9611->regmap, 0x829e, 0xf7);
405 regmap_write(lt9611->regmap, 0x8204, 0xff);
406 regmap_write(lt9611->regmap, 0x8204, 0xfe);
416 regmap_read(lt9611->regmap, 0x8203, &val);
418 val &= ~0xc0;
419 regmap_write(lt9611->regmap, 0x8203, val);
420 regmap_write(lt9611->regmap, 0x8207, 0xff); /* clear */
421 regmap_write(lt9611->regmap, 0x8207, 0x3f);
427 { 0x8024, 0x76 },
428 { 0x8023, 0x01 },
429 { 0x8157, 0x03 }, /* set addr pin as output */
430 { 0x8149, 0x0b },
432 { 0x8102, 0x48 }, /* MIPI Rx power down */
433 { 0x8123, 0x80 },
434 { 0x8130, 0x00 },
435 { 0x8011, 0x0a },
448 { 0x8101, 0x18 }, /* sel xtal clock */
451 { 0x821b, 0x69 }, /* timer 2 */
452 { 0x821c, 0x78 },
453 { 0x82cb, 0x69 }, /* timer 1 */
454 { 0x82cc, 0x78 },
457 { 0x8251, 0x01 },
458 { 0x8258, 0x0a }, /* hpd irq */
459 { 0x8259, 0x80 }, /* hpd debounce width */
460 { 0x829e, 0xf7 }, /* video check irq */
463 { 0x8004, 0xf0 },
464 { 0x8006, 0xf0 },
465 { 0x800a, 0x80 },
466 { 0x800b, 0x40 },
467 { 0x800d, 0xef },
468 { 0x8011, 0xfa },
472 return 0;
485 ret = regmap_write(lt9611->regmap, 0x8130, 0x6a);
497 gpiod_set_value_cansleep(lt9611->reset_gpio, 0);
517 lt9611->supplies[0].supply = "vdd";
521 if (ret < 0)
524 return regulator_set_load(lt9611->supplies[0].consumer, 300000);
531 ret = regulator_enable(lt9611->supplies[0].consumer);
532 if (ret < 0)
538 if (ret < 0) {
539 regulator_disable(lt9611->supplies[0].consumer);
543 return 0;
550 unsigned int reg_val = 0;
551 int connected = 0;
553 regmap_read(lt9611->regmap, 0x825e, ®_val);
554 connected = (reg_val & (BIT(2) | BIT(0)));
565 int ret = 0;
569 memset(lt9611->edid_buf, 0, sizeof(lt9611->edid_buf));
571 regmap_write(lt9611->regmap, 0x8503, 0xc9);
573 /* 0xA0 is EDID device address */
574 regmap_write(lt9611->regmap, 0x8504, 0xa0);
575 /* 0x00 is EDID offset address */
576 regmap_write(lt9611->regmap, 0x8505, 0x00);
579 regmap_write(lt9611->regmap, 0x8506, EDID_LEN);
580 regmap_write(lt9611->regmap, 0x8514, 0x7f);
582 for (i = 0; i < EDID_LOOP; i++) {
584 regmap_write(lt9611->regmap, 0x8505, i * EDID_LEN);
585 regmap_write(lt9611->regmap, 0x8507, 0x36);
586 regmap_write(lt9611->regmap, 0x8507, 0x31);
587 regmap_write(lt9611->regmap, 0x8507, 0x37);
590 regmap_read(lt9611->regmap, 0x8540, &temp);
593 for (j = 0; j < EDID_LEN; j++) {
594 regmap_read(lt9611->regmap, 0x8583, &temp);
611 regmap_write(lt9611->regmap, 0x8507, 0x1f);
629 if (block == 0) {
640 return 0;
688 regmap_write(lt9611->regmap, 0x8130, 0xea);
698 ret = regmap_write(lt9611->regmap, 0x8130, 0x6a);
713 const struct mipi_dsi_device_info info = { "lt9611", 0, lt9611->dev->of_node};
735 if (ret < 0) {
773 { 0x8102, 0x12 },
774 { 0x8123, 0x40 },
775 { 0x8130, 0xea },
776 { 0x8011, 0xfa },
824 *num_input_fmts = 0;
832 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
840 * - 0x01, 0x84df
841 * - 0x04, 0x84c0
843 #define LT9611_INFOFRAME_AUDIO 0x02
844 #define LT9611_INFOFRAME_AVI 0x08
845 #define LT9611_INFOFRAME_SPD 0x10
846 #define LT9611_INFOFRAME_VENDOR 0x20
873 mask = 0;
878 regmap_update_bits(lt9611->regmap, 0x843d, mask, 0);
880 return 0;
894 addr = 0x84b2;
899 addr = 0x8440;
904 addr = 0x8493;
909 addr = 0x8474;
914 mask = 0;
919 for (i = 0; i < len; i++)
922 regmap_update_bits(lt9611->regmap, 0x843d, mask, mask);
925 return 0;
945 regmap_write(lt9611->regmap, 0x82d6, 0x8c);
946 regmap_write(lt9611->regmap, 0x82d7, 0x04);
948 regmap_write(lt9611->regmap, 0x8406, 0x08);
949 regmap_write(lt9611->regmap, 0x8407, 0x10);
951 regmap_write(lt9611->regmap, 0x8434, 0xd5);
953 return 0;
964 regmap_write(lt9611->regmap, 0x840f, 0x2b);
966 regmap_write(lt9611->regmap, 0x840f, 0xab);
970 regmap_write(lt9611->regmap, 0x8435, 0x00);
971 regmap_write(lt9611->regmap, 0x8436, 0x18);
972 regmap_write(lt9611->regmap, 0x8437, 0x00);
985 regmap_write(lt9611->regmap, 0x8406, 0x00);
986 regmap_write(lt9611->regmap, 0x8407, 0x00);
1017 lt9611->dsi0_node = of_graph_get_remote_node(dev->of_node, 0, -1);
1047 return 0;
1055 regmap_write(lt9611->regmap, 0x80ee, 0x01);
1056 ret = regmap_read(lt9611->regmap, 0x8002, &rev);
1060 dev_info(lt9611->dev, "LT9611 revision: 0x%x\n", rev);
1098 if (ret < 0)
1102 if (ret < 0)
1130 regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_AUDIO, 0);
1163 return 0;