Lines Matching +full:92 +full:mhz
73 #define MHZ(x) ((x) * 1000000UL) macro
75 #define REF_CLK_RATE_MAX MHZ(64)
76 #define REF_CLK_RATE_MIN MHZ(2)
77 #define FOUT_MAX MHZ(1250)
78 #define FOUT_MIN MHZ(40)
79 #define FVCO_DIV_FACTOR MHZ(80)
249 /* limitation: 2MHz <= Fin / N <= 8MHz */ in dphy_pll_get_configure_from_opts()
250 min_n = DIV_ROUND_UP_ULL((u64)fin, MHZ(8)); in dphy_pll_get_configure_from_opts()
251 max_n = DIV_ROUND_DOWN_ULL((u64)fin, MHZ(2)); in dphy_pll_get_configure_from_opts()
317 return (clk_get_rate(dsi->clk_cfg) / MHZ(1) - 17) * 4; in dphy_pll_get_cfgclkrange()
323 unsigned long mbps = dphy_opts->hs_clk_rate / MHZ(1); in dphy_pll_get_hsfreqrange()
335 unsigned long fout = data_rate_to_fout(dphy_opts->hs_clk_rate) / MHZ(1); in dphy_pll_get_vco()
347 unsigned long fout = data_rate_to_fout(dphy_opts->hs_clk_rate) / MHZ(1); in dphy_pll_get_prop()
771 HSTT(1850, 223, 92, 175, 54),