Lines Matching +full:vga +full:- +full:connector
1 // SPDX-License-Identifier: GPL-2.0-only
204 struct drm_connector connector; member
208 container_of(x, struct ch7033_priv, connector)
214 struct drm_connector *connector, bool force) in ch7033_connector_detect() argument
216 struct ch7033_priv *priv = conn_to_ch7033_priv(connector); in ch7033_connector_detect()
218 return drm_bridge_detect(priv->next_bridge); in ch7033_connector_detect()
230 static int ch7033_connector_get_modes(struct drm_connector *connector) in ch7033_connector_get_modes() argument
232 struct ch7033_priv *priv = conn_to_ch7033_priv(connector); in ch7033_connector_get_modes()
236 drm_edid = drm_bridge_edid_read(priv->next_bridge, connector); in ch7033_connector_get_modes()
237 drm_edid_connector_update(connector, drm_edid); in ch7033_connector_get_modes()
239 ret = drm_edid_connector_add_modes(connector); in ch7033_connector_get_modes()
242 ret = drm_add_modes_noedid(connector, 1920, 1080); in ch7033_connector_get_modes()
243 drm_set_preferred_mode(connector, 1024, 768); in ch7033_connector_get_modes()
250 struct drm_connector *connector) in ch7033_connector_best_encoder() argument
252 struct ch7033_priv *priv = conn_to_ch7033_priv(connector); in ch7033_connector_best_encoder()
254 return priv->bridge.encoder; in ch7033_connector_best_encoder()
266 if (priv->bridge.dev) in ch7033_hpd_event()
267 drm_helper_hpd_irq_event(priv->connector.dev); in ch7033_hpd_event()
274 struct drm_connector *connector = &priv->connector; in ch7033_bridge_attach() local
277 ret = drm_bridge_attach(bridge->encoder, priv->next_bridge, bridge, in ch7033_bridge_attach()
285 if (priv->next_bridge->ops & DRM_BRIDGE_OP_DETECT) { in ch7033_bridge_attach()
286 connector->polled = DRM_CONNECTOR_POLL_HPD; in ch7033_bridge_attach()
288 connector->polled = DRM_CONNECTOR_POLL_CONNECT | in ch7033_bridge_attach()
292 if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) { in ch7033_bridge_attach()
293 drm_bridge_hpd_enable(priv->next_bridge, ch7033_hpd_event, in ch7033_bridge_attach()
297 drm_connector_helper_add(connector, in ch7033_bridge_attach()
299 ret = drm_connector_init_with_ddc(bridge->dev, &priv->connector, in ch7033_bridge_attach()
301 priv->next_bridge->type, in ch7033_bridge_attach()
302 priv->next_bridge->ddc); in ch7033_bridge_attach()
304 DRM_ERROR("Failed to initialize connector\n"); in ch7033_bridge_attach()
308 return drm_connector_attach_encoder(&priv->connector, bridge->encoder); in ch7033_bridge_attach()
315 if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) in ch7033_bridge_detach()
316 drm_bridge_hpd_disable(priv->next_bridge); in ch7033_bridge_detach()
317 drm_connector_cleanup(&priv->connector); in ch7033_bridge_detach()
324 if (mode->clock > 165000) in ch7033_bridge_mode_valid()
326 if (mode->hdisplay >= 1920) in ch7033_bridge_mode_valid()
328 if (mode->vdisplay >= 1080) in ch7033_bridge_mode_valid()
337 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_disable()
338 regmap_update_bits(priv->regmap, 0x52, RESETDB, 0x00); in ch7033_bridge_disable()
345 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_enable()
346 regmap_update_bits(priv->regmap, 0x52, RESETDB, RESETDB); in ch7033_bridge_enable()
354 int hbporch = mode->hsync_start - mode->hdisplay; in ch7033_bridge_mode_set()
355 int hsynclen = mode->hsync_end - mode->hsync_start; in ch7033_bridge_mode_set()
356 int vbporch = mode->vsync_start - mode->vdisplay; in ch7033_bridge_mode_set()
357 int vsynclen = mode->vsync_end - mode->vsync_start; in ch7033_bridge_mode_set()
362 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_mode_set()
365 regmap_write(priv->regmap, 0x52, 0x00); in ch7033_bridge_mode_set()
367 regmap_write(priv->regmap, 0x52, RESETIB); in ch7033_bridge_mode_set()
372 regmap_write(priv->regmap, 0x03, 0x00); in ch7033_bridge_mode_set()
375 regmap_update_bits(priv->regmap, 0x07, DRI_PD | IO_PD, 0); in ch7033_bridge_mode_set()
376 regmap_update_bits(priv->regmap, 0x08, DRI_PDDRI | PDDAC | PANEN, 0); in ch7033_bridge_mode_set()
377 regmap_update_bits(priv->regmap, 0x09, DPD | GCKOFF | in ch7033_bridge_mode_set()
379 regmap_update_bits(priv->regmap, 0x0a, HD_DVIB, 0); in ch7033_bridge_mode_set()
382 regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 | in ch7033_bridge_mode_set()
383 (mode->hdisplay >> 8)); in ch7033_bridge_mode_set()
384 regmap_write(priv->regmap, 0x0c, mode->hdisplay); in ch7033_bridge_mode_set()
385 regmap_write(priv->regmap, 0x0d, mode->htotal); in ch7033_bridge_mode_set()
386 regmap_write(priv->regmap, 0x0e, (hsynclen >> 8) << 3 | in ch7033_bridge_mode_set()
388 regmap_write(priv->regmap, 0x0f, hbporch); in ch7033_bridge_mode_set()
389 regmap_write(priv->regmap, 0x10, hsynclen); in ch7033_bridge_mode_set()
392 regmap_write(priv->regmap, 0x11, (mode->vtotal >> 8) << 3 | in ch7033_bridge_mode_set()
393 (mode->vdisplay >> 8)); in ch7033_bridge_mode_set()
394 regmap_write(priv->regmap, 0x12, mode->vdisplay); in ch7033_bridge_mode_set()
395 regmap_write(priv->regmap, 0x13, mode->vtotal); in ch7033_bridge_mode_set()
396 regmap_write(priv->regmap, 0x14, ((vsynclen >> 8) << 3) | in ch7033_bridge_mode_set()
398 regmap_write(priv->regmap, 0x15, vbporch); in ch7033_bridge_mode_set()
399 regmap_write(priv->regmap, 0x16, vsynclen); in ch7033_bridge_mode_set()
402 regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); in ch7033_bridge_mode_set()
405 regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16); in ch7033_bridge_mode_set()
406 regmap_update_bits(priv->regmap, 0x19, HPO_I | VPO_I | GCLKFREQ, in ch7033_bridge_mode_set()
407 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0 | in ch7033_bridge_mode_set()
408 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0 | in ch7033_bridge_mode_set()
409 mode->clock >> 16); in ch7033_bridge_mode_set()
410 regmap_write(priv->regmap, 0x1a, mode->clock >> 8); in ch7033_bridge_mode_set()
411 regmap_write(priv->regmap, 0x1b, mode->clock); in ch7033_bridge_mode_set()
414 regmap_write(priv->regmap, 0x1f, (mode->htotal >> 8) << 3 | in ch7033_bridge_mode_set()
415 (mode->hdisplay >> 8)); in ch7033_bridge_mode_set()
416 regmap_write(priv->regmap, 0x20, mode->hdisplay); in ch7033_bridge_mode_set()
417 regmap_write(priv->regmap, 0x21, mode->htotal); in ch7033_bridge_mode_set()
420 regmap_write(priv->regmap, 0x25, (mode->vtotal >> 8) << 3 | in ch7033_bridge_mode_set()
421 (mode->vdisplay >> 8)); in ch7033_bridge_mode_set()
422 regmap_write(priv->regmap, 0x26, mode->vdisplay); in ch7033_bridge_mode_set()
423 regmap_write(priv->regmap, 0x27, mode->vtotal); in ch7033_bridge_mode_set()
425 /* VGA channel bypass */ in ch7033_bridge_mode_set()
426 regmap_update_bits(priv->regmap, 0x2b, VFMT, 9); in ch7033_bridge_mode_set()
429 regmap_update_bits(priv->regmap, 0x2e, HPO_O | VPO_O, in ch7033_bridge_mode_set()
430 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0 | in ch7033_bridge_mode_set()
431 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0); in ch7033_bridge_mode_set()
434 regmap_update_bits(priv->regmap, 0x54, HWO_HDMI_HI | HOO_HDMI_HI, in ch7033_bridge_mode_set()
437 regmap_write(priv->regmap, 0x55, hbporch); in ch7033_bridge_mode_set()
438 regmap_write(priv->regmap, 0x56, hsynclen); in ch7033_bridge_mode_set()
441 regmap_update_bits(priv->regmap, 0x57, VWO_HDMI_HI | VOO_HDMI_HI, in ch7033_bridge_mode_set()
444 regmap_write(priv->regmap, 0x58, vbporch); in ch7033_bridge_mode_set()
445 regmap_write(priv->regmap, 0x59, vsynclen); in ch7033_bridge_mode_set()
448 regmap_update_bits(priv->regmap, 0x7e, HDMI_LVDS_SEL, HDMI_LVDS_SEL); in ch7033_bridge_mode_set()
453 regmap_write(priv->regmap, 0x03, 0x01); in ch7033_bridge_mode_set()
455 /* No idea what these do, but VGA is wobbly and blinky without them. */ in ch7033_bridge_mode_set()
456 regmap_update_bits(priv->regmap, 0x07, CKINV, CKINV); in ch7033_bridge_mode_set()
457 regmap_update_bits(priv->regmap, 0x08, DISPON, DISPON); in ch7033_bridge_mode_set()
460 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_DIVSEL, DRI_PLL_DIVSEL); in ch7033_bridge_mode_set()
461 if (mode->clock <= 40000) { in ch7033_bridge_mode_set()
462 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 | in ch7033_bridge_mode_set()
467 } else if (mode->clock < 80000) { in ch7033_bridge_mode_set()
468 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 | in ch7033_bridge_mode_set()
475 regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 | in ch7033_bridge_mode_set()
483 /* This seems to be color calibration for VGA. */ in ch7033_bridge_mode_set()
484 regmap_write(priv->regmap, 0x64, 0x29); /* LSB Blue */ in ch7033_bridge_mode_set()
485 regmap_write(priv->regmap, 0x65, 0x29); /* LSB Green */ in ch7033_bridge_mode_set()
486 regmap_write(priv->regmap, 0x66, 0x29); /* LSB Red */ in ch7033_bridge_mode_set()
487 regmap_write(priv->regmap, 0x67, 0x00); /* MSB Blue */ in ch7033_bridge_mode_set()
488 regmap_write(priv->regmap, 0x68, 0x00); /* MSB Green */ in ch7033_bridge_mode_set()
489 regmap_write(priv->regmap, 0x69, 0x00); /* MSB Red */ in ch7033_bridge_mode_set()
491 regmap_update_bits(priv->regmap, 0x6b, DRI_PD_SER, 0x00); in ch7033_bridge_mode_set()
492 regmap_update_bits(priv->regmap, 0x6c, DRI_PLL_PD, 0x00); in ch7033_bridge_mode_set()
497 regmap_write(priv->regmap, 0x03, 0x03); in ch7033_bridge_mode_set()
500 regmap_update_bits(priv->regmap, 0x28, VGACLK_BP | HM_LV_SEL, in ch7033_bridge_mode_set()
502 regmap_update_bits(priv->regmap, 0x2a, HDMICLK_BP | HDMI_BP, in ch7033_bridge_mode_set()
508 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_mode_set()
511 regmap_write(priv->regmap, 0x10, mode->clock >> 16); in ch7033_bridge_mode_set()
512 regmap_write(priv->regmap, 0x11, mode->clock >> 8); in ch7033_bridge_mode_set()
513 regmap_write(priv->regmap, 0x12, mode->clock); in ch7033_bridge_mode_set()
533 struct device *dev = &client->dev; in ch7033_probe()
540 return -ENOMEM; in ch7033_probe()
544 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1, NULL, in ch7033_probe()
545 &priv->next_bridge); in ch7033_probe()
549 priv->regmap = devm_regmap_init_i2c(client, &ch7033_regmap_config); in ch7033_probe()
550 if (IS_ERR(priv->regmap)) { in ch7033_probe()
551 dev_err(&client->dev, "regmap init failed\n"); in ch7033_probe()
552 return PTR_ERR(priv->regmap); in ch7033_probe()
555 ret = regmap_read(priv->regmap, 0x00, &val); in ch7033_probe()
557 dev_err(&client->dev, "error reading the model id: %d\n", ret); in ch7033_probe()
561 dev_err(&client->dev, "the device is not a ch7033\n"); in ch7033_probe()
562 return -ENODEV; in ch7033_probe()
565 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_probe()
566 ret = regmap_read(priv->regmap, 0x51, &val); in ch7033_probe()
568 dev_err(&client->dev, "error reading the model id: %d\n", ret); in ch7033_probe()
572 dev_err(&client->dev, "unknown revision %u\n", val); in ch7033_probe()
573 return -ENODEV; in ch7033_probe()
576 INIT_LIST_HEAD(&priv->bridge.list); in ch7033_probe()
577 priv->bridge.funcs = &ch7033_bridge_funcs; in ch7033_probe()
578 priv->bridge.of_node = dev->of_node; in ch7033_probe()
579 drm_bridge_add(&priv->bridge); in ch7033_probe()
587 struct device *dev = &client->dev; in ch7033_remove()
590 drm_bridge_remove(&priv->bridge); in ch7033_remove()