Lines Matching refs:chipone_writeb
245 static int chipone_writeb(struct chipone *icn, u8 reg, u8 val)
337 chipone_writeb(icn, PLL_CTRL(6),
339 chipone_writeb(icn, PLL_REF_DIV, ref_div);
340 chipone_writeb(icn, PLL_INT(0), best_m);
372 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C);
374 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);
376 chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff);
378 chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff);
384 chipone_writeb(icn, VACTIVE_HACTIVE_HI,
392 chipone_writeb(icn, HFP_LI, hfp & 0xff);
393 chipone_writeb(icn, HSYNC_LI, hsync & 0xff);
394 chipone_writeb(icn, HBP_LI, hbp & 0xff);
396 chipone_writeb(icn, HFP_HSW_HBP_HI,
401 chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay);
403 chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start);
405 chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end);
408 chipone_writeb(icn, SYNC_EVENT_DLY, 0x80);
409 chipone_writeb(icn, HFP_MIN, hfp & 0xff);
412 chipone_writeb(icn, DSI_CTRL,
415 chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0);
416 chipone_writeb(icn, PLL_CTRL(12), 0xff);
417 chipone_writeb(icn, MIPI_PN_SWAP, 0x00);
423 chipone_writeb(icn, BIST_POL, pol);
428 chipone_writeb(icn, SYS_CTRL(0), 0x40);
436 chipone_writeb(icn, SYS_CTRL(1), sys_ctrl_1);
439 chipone_writeb(icn, MIPI_FORCE_0, 0x20);
440 chipone_writeb(icn, PLL_CTRL(1), 0x20);
441 chipone_writeb(icn, CONFIG_FINISH, 0x10);