Lines Matching +full:gpio +full:- +full:out +full:- +full:pol
1 // SPDX-License-Identifier: GPL-2.0+
16 #include <linux/gpio/consumer.h>
18 #include <linux/media-bus-format.h>
214 return ret == val_size ? 0 : -EINVAL;
240 ret = regmap_read(icn->regmap, reg, &pval);
247 return regmap_write(icn->regmap, reg, val);
254 unsigned int mode_clock = mode->clock * 1000;
271 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider
274 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider
276 * It seems the PLL input clock after applying P pre-divider have
279 if (icn->refclk)
280 fin = icn->refclk_rate;
282 fin = icn->dsi->hs_rate / 4; /* in Hz */
311 /* Apply post-divider */
314 delta = abs(mode_clock - freq_out);
326 dev_dbg(icn->dev,
329 min_delta, icn->refclk ? "EXT" : "DSI", fin,
333 if (best_p_pot) /* Prefer /2 pre-divider */
338 icn->refclk ? PLL_CTRL_6_EXTERNAL : PLL_CTRL_6_MIPI_CLK);
347 struct drm_display_mode *mode = &icn->mode;
351 u8 pol, sys_ctrl_1, id[4];
358 dev_dbg(icn->dev,
363 dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n");
369 bus_flags = bridge_state->output_bus_cfg.flags;
371 if (icn->interface_i2c)
376 chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff);
378 chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff);
385 ((mode->hdisplay >> 8) & 0xf) |
386 (((mode->vdisplay >> 8) & 0xf) << 4));
388 hfp = mode->hsync_start - mode->hdisplay;
389 hsync = mode->hsync_end - mode->hsync_start;
390 hbp = mode->htotal - mode->hsync_end;
401 chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay);
403 chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start);
405 chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end);
413 DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1));
420 pol = ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIST_POL_HSYNC_POL : 0) |
421 ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIST_POL_VSYNC_POL : 0) |
423 chipone_writeb(icn, BIST_POL, pol);
452 if (icn->vdd1) {
453 ret = regulator_enable(icn->vdd1);
455 DRM_DEV_ERROR(icn->dev,
459 if (icn->vdd2) {
460 ret = regulator_enable(icn->vdd2);
462 DRM_DEV_ERROR(icn->dev,
466 if (icn->vdd3) {
467 ret = regulator_enable(icn->vdd3);
469 DRM_DEV_ERROR(icn->dev,
473 ret = clk_prepare_enable(icn->refclk);
475 DRM_DEV_ERROR(icn->dev,
478 gpiod_set_value(icn->enable_gpio, 1);
488 clk_disable_unprepare(icn->refclk);
490 if (icn->vdd1)
491 regulator_disable(icn->vdd1);
493 if (icn->vdd2)
494 regulator_disable(icn->vdd2);
496 if (icn->vdd3)
497 regulator_disable(icn->vdd3);
499 gpiod_set_value(icn->enable_gpio, 0);
508 drm_mode_copy(&icn->mode, adjusted_mode);
513 struct mipi_dsi_device *dsi = icn->dsi;
514 struct device *dev = icn->dev;
517 dsi_lanes = drm_of_get_data_lanes_count_ep(dev->of_node, 0, 0, 1, 4);
520 * If the 'data-lanes' property does not exist in DT or is invalid,
521 * default to previously hard-coded behavior, which was 4 data lanes.
524 icn->dsi->lanes = 4;
526 icn->dsi->lanes = dsi_lanes;
528 dsi->format = MIPI_DSI_FMT_RGB888;
529 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
531 dsi->hs_rate = 500000000;
532 dsi->lp_rate = 16000000;
536 dev_err(icn->dev, "failed to attach dsi\n");
543 struct device *dev = icn->dev;
556 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
561 return -EINVAL;
566 return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n");
574 icn->dsi = dsi;
587 return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags);
609 /* This is the DSI-end bus format */
630 struct device *dev = icn->dev;
633 icn->refclk = devm_clk_get_optional(dev, "refclk");
634 if (IS_ERR(icn->refclk)) {
635 ret = PTR_ERR(icn->refclk);
638 } else if (icn->refclk) {
639 icn->refclk_rate = clk_get_rate(icn->refclk);
640 if (icn->refclk_rate < 10000000 || icn->refclk_rate > 154000000) {
641 DRM_DEV_ERROR(dev, "REFCLK out of range: %ld Hz\n",
642 icn->refclk_rate);
643 return -EINVAL;
647 icn->vdd1 = devm_regulator_get_optional(dev, "vdd1");
648 if (IS_ERR(icn->vdd1)) {
649 ret = PTR_ERR(icn->vdd1);
650 if (ret == -EPROBE_DEFER)
651 return -EPROBE_DEFER;
652 icn->vdd1 = NULL;
656 icn->vdd2 = devm_regulator_get_optional(dev, "vdd2");
657 if (IS_ERR(icn->vdd2)) {
658 ret = PTR_ERR(icn->vdd2);
659 if (ret == -EPROBE_DEFER)
660 return -EPROBE_DEFER;
661 icn->vdd2 = NULL;
665 icn->vdd3 = devm_regulator_get_optional(dev, "vdd3");
666 if (IS_ERR(icn->vdd3)) {
667 ret = PTR_ERR(icn->vdd3);
668 if (ret == -EPROBE_DEFER)
669 return -EPROBE_DEFER;
670 icn->vdd3 = NULL;
674 icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
675 if (IS_ERR(icn->enable_gpio)) {
676 DRM_DEV_ERROR(dev, "failed to get enable GPIO\n");
677 return PTR_ERR(icn->enable_gpio);
680 icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
681 if (IS_ERR(icn->panel_bridge))
682 return PTR_ERR(icn->panel_bridge);
694 return -ENOMEM;
696 icn->dev = dev;
702 icn->bridge.funcs = &chipone_bridge_funcs;
703 icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
704 icn->bridge.of_node = dev->of_node;
713 struct device *dev = &dsi->dev;
721 icn->regmap = devm_regmap_init(dev, &chipone_dsi_regmap_bus,
723 if (IS_ERR(icn->regmap))
724 return PTR_ERR(icn->regmap);
726 icn->interface_i2c = false;
727 icn->dsi = dsi;
731 drm_bridge_add(&icn->bridge);
735 drm_bridge_remove(&icn->bridge);
742 struct device *dev = &client->dev;
750 icn->regmap = devm_regmap_init_i2c(client, &chipone_regmap_config);
751 if (IS_ERR(icn->regmap))
752 return PTR_ERR(icn->regmap);
754 icn->interface_i2c = true;
755 icn->client = client;
759 drm_bridge_add(&icn->bridge);
769 drm_bridge_remove(&icn->bridge);
782 .name = "chipone-icn6211",
797 .name = "chipone-icn6211-i2c",
821 MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge");