Lines Matching +full:2 +full:x32 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Loading OCM re-trying times */
50 #define INTR_SOFTWARE_INT BIT(3)
51 #define INTR_RECEIVED_MSG BIT(5)
63 #define STORE_AN BIT(7)
64 #define RX_REPEATER BIT(6)
65 #define RE_AUTHEN BIT(5)
66 #define SW_AUTH_OK BIT(4)
67 #define HARD_AUTH_EN BIT(3)
68 #define ENC_EN BIT(2)
69 #define BKSV_SRM_PASS BIT(1)
70 #define KSVLIST_VLD BIT(0)
75 #define HDCP2TX_FW_EN BIT(4)
112 #define SP_TX_H_SYNC_STA_H 0x32
138 /* HPD debounce time 2ms for 27M clock */
149 #define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2)
153 #define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */
159 #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */
161 #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */
163 #define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */
165 #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */
167 #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */
189 #define FLASH_LOAD_STA_CHK BIT(7)
192 /* bit positions */
193 #define FLASH_DONE BIT(7)
194 #define BOOT_LOAD_DONE BIT(6)
195 #define CRC_OK BIT(5)
196 #define LOAD_DONE BIT(4)
197 #define O_RW_DONE BIT(3)
198 #define FUSE_BUSY BIT(2)
199 #define DECRYPT_EN BIT(1)
200 #define LOAD_START BIT(0)
205 #define FLASH_LEN_LOW 0x32
207 /* bit positions */
208 #define READ_DELAY_SELECT BIT(7)
209 #define GENERAL_INSTRUCTION_EN BIT(6)
210 #define FLASH_ERASE_EN BIT(5)
211 #define RDID_READ_EN BIT(4)
212 #define REMS_READ_EN BIT(3)
213 #define WRITE_STATUS_EN BIT(2)
214 #define FLASH_READ BIT(1)
215 #define FLASH_WRITE BIT(0)
221 /* bit field positions */
223 /* bit field values */
230 #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */
234 #define OCM_FW_REVERSION 0x32
240 /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */
251 #define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd))
253 /* Bit 0&1: 3D video structure */
254 /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */
256 #define AP_VIDEO_CHG BIT(2)
257 #define AP_AUDIO_CHG BIT(3)
258 #define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */
259 #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */
260 #define AP_DISABLE_PD BIT(6)
261 #define AP_DISABLE_DISPLAY BIT(7)
264 #define HPD_SOURCE BIT(6)
274 #define MIPI_CLK_DET_DET_BYPASS 2
299 /* Bit[7:6]: VCO band control, only effective */
304 /* Bit[1:0]: test point output select - */
312 /* Bit[5:4]: VCO metal capacitance - */
313 /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */
316 #define MIPI_PLL_PLL_LDO_BIT 2
317 /* Bit[3:2]: vco_v2i power - */
324 /* This bit itself is S/C, and it clears 0x84:0x31[7] */
328 /* This bit is cleared by 0x84:0x2D[7] */
334 #define MIPI_FRQ_COUNTER_RST 2
336 /* Bit 0 is reserved */
346 /* Bit 2 is reserved */
363 /* For DSC only; note: bit[7:6] are reserved */
370 /* Bit[2:0] are reserved */