Lines Matching +full:0 +full:x84
16 #define TX_P0_ADDR 0x70
17 #define TX_P1_ADDR 0x7A
18 #define TX_P2_ADDR 0x72
20 #define RX_P0_ADDR 0x7e
21 #define RX_P1_ADDR 0x84
22 #define RX_P2_ADDR 0x54
24 #define RSVD_00_ADDR 0x00
25 #define RSVD_D1_ADDR 0xD1
26 #define RSVD_60_ADDR 0x60
27 #define RSVD_39_ADDR 0x39
28 #define RSVD_7F_ADDR 0x7F
30 #define TCPC_INTERFACE_ADDR 0x58
44 /* Register definition of device address 0x58 */
46 #define PRODUCT_ID_L 0x02
47 #define PRODUCT_ID_H 0x03
49 #define INTR_ALERT_1 0xCC
53 #define SYSTEM_STSTUS 0x45
54 #define INTERFACE_CHANGE_INT 0x44
55 #define HPD_STATUS_CHANGE 0x80
56 #define HPD_STATUS 0x80
58 /******** END of I2C Address 0x58 ********/
61 /* Register definition of device address 0x70 */
62 #define TX_HDCP_CTRL0 0x01
70 #define KSVLIST_VLD BIT(0)
72 #define SP_TX_WAIT_R0_TIME 0x40
73 #define SP_TX_WAIT_KSVR_TIME 0x42
74 #define SP_TX_SYS_CTRL1_REG 0x80
77 #define SP_TX_LINK_BW_SET_REG 0xA0
78 #define SP_TX_LANE_COUNT_SET_REG 0xA1
80 #define M_VID_0 0xC0
81 #define M_VID_1 0xC1
82 #define M_VID_2 0xC2
83 #define N_VID_0 0xC3
84 #define N_VID_1 0xC4
85 #define N_VID_2 0xC5
87 #define KEY_START_ADDR 0x9000
94 /* Register definition of device address 0x72 */
95 #define AUX_RST 0x04
96 #define RST_CTRL2 0x07
98 #define SP_TX_TOTAL_LINE_STA_L 0x24
99 #define SP_TX_TOTAL_LINE_STA_H 0x25
100 #define SP_TX_ACT_LINE_STA_L 0x26
101 #define SP_TX_ACT_LINE_STA_H 0x27
102 #define SP_TX_V_F_PORCH_STA 0x28
103 #define SP_TX_V_SYNC_STA 0x29
104 #define SP_TX_V_B_PORCH_STA 0x2A
105 #define SP_TX_TOTAL_PIXEL_STA_L 0x2B
106 #define SP_TX_TOTAL_PIXEL_STA_H 0x2C
107 #define SP_TX_ACT_PIXEL_STA_L 0x2D
108 #define SP_TX_ACT_PIXEL_STA_H 0x2E
109 #define SP_TX_H_F_PORCH_STA_L 0x2F
110 #define SP_TX_H_F_PORCH_STA_H 0x30
111 #define SP_TX_H_SYNC_STA_L 0x31
112 #define SP_TX_H_SYNC_STA_H 0x32
113 #define SP_TX_H_B_PORCH_STA_L 0x33
114 #define SP_TX_H_B_PORCH_STA_H 0x34
116 #define SP_TX_VID_CTRL 0x84
117 #define SP_TX_BPC_MASK 0xE0
118 #define SP_TX_BPC_6 0x00
119 #define SP_TX_BPC_8 0x20
120 #define SP_TX_BPC_10 0x40
121 #define SP_TX_BPC_12 0x60
123 #define VIDEO_BIT_MATRIX_12 0x4c
125 #define AUDIO_CHANNEL_STATUS_1 0xd0
126 #define AUDIO_CHANNEL_STATUS_2 0xd1
127 #define AUDIO_CHANNEL_STATUS_3 0xd2
128 #define AUDIO_CHANNEL_STATUS_4 0xd3
129 #define AUDIO_CHANNEL_STATUS_5 0xd4
130 #define AUDIO_CHANNEL_STATUS_6 0xd5
131 #define TDM_SLAVE_MODE 0x10
132 #define I2S_SLAVE_MODE 0x08
133 #define AUDIO_LAYOUT 0x01
135 #define HPD_DET_TIMER_BIT0_7 0xea
136 #define HPD_DET_TIMER_BIT8_15 0xeb
137 #define HPD_DET_TIMER_BIT16_23 0xec
141 #define AUDIO_CONTROL_REGISTER 0xe6
142 #define TDM_TIMING_MODE 0x08
144 #define I2C_ADDR_72_DPTX 0x72
150 #define VIDEO_CONTROL_0 0x08
152 #define ACTIVE_LINES_L 0x14
153 #define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */
154 #define VERTICAL_FRONT_PORCH 0x16
155 #define VERTICAL_SYNC_WIDTH 0x17
156 #define VERTICAL_BACK_PORCH 0x18
158 #define HORIZONTAL_TOTAL_PIXELS_L 0x19
159 #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */
160 #define HORIZONTAL_ACTIVE_PIXELS_L 0x1B
161 #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */
162 #define HORIZONTAL_FRONT_PORCH_L 0x1D
163 #define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */
164 #define HORIZONTAL_SYNC_WIDTH_L 0x1F
165 #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */
166 #define HORIZONTAL_BACK_PORCH_L 0x21
167 #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */
169 /******** END of I2C Address 0x72 *********/
172 /* Register definition of device address 0x7a */
173 #define DP_TX_SWING_REG_CNT 0x14
174 #define DP_TX_LANE0_SWING_REG0 0x00
175 #define DP_TX_LANE1_SWING_REG0 0x14
176 /******** END of I2C Address 0x7a *********/
179 /* Register definition of device address 0x7e */
181 #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E
183 #define R_BOOT_RETRY 0x00
184 #define R_RAM_ADDR_H 0x01
185 #define R_RAM_ADDR_L 0x02
186 #define R_RAM_LEN_H 0x03
187 #define R_RAM_LEN_L 0x04
188 #define FLASH_LOAD_STA 0x05
191 #define R_RAM_CTRL 0x05
200 #define LOAD_START BIT(0)
202 #define FLASH_ADDR_HIGH 0x0F
203 #define FLASH_ADDR_LOW 0x10
204 #define FLASH_LEN_HIGH 0x31
205 #define FLASH_LEN_LOW 0x32
206 #define R_FLASH_RW_CTRL 0x33
215 #define FLASH_WRITE BIT(0)
217 #define FLASH_BUF_BASE_ADDR 0x60
218 #define FLASH_BUF_LEN 0x20
220 #define XTAL_FRQ_SEL 0x3F
224 #define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS)
227 #define R_DSC_CTRL_0 0x40
229 #define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */
231 #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */
233 #define OCM_FW_VERSION 0x31
234 #define OCM_FW_REVERSION 0x32
236 #define AP_AUX_ADDR_7_0 0x11
237 #define AP_AUX_ADDR_15_8 0x12
238 #define AP_AUX_ADDR_19_16 0x13
240 /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */
241 #define AP_AUX_CTRL_STATUS 0x14
242 #define AP_AUX_CTRL_OP_EN 0x10
243 #define AP_AUX_CTRL_ADDRONLY 0x20
245 #define AP_AUX_BUFF_START 0x15
246 #define PIXEL_CLOCK_L 0x25
247 #define PIXEL_CLOCK_H 0x26
249 #define AP_AUX_COMMAND 0x27 /* com+len */
253 /* Bit 0&1: 3D video structure */
254 /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */
255 #define AP_AV_STATUS 0x28
258 #define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */
259 #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */
263 #define GPIO_CTRL_2 0x49
267 /* Register definition of device address 0x84 */
268 #define MIPI_PHY_CONTROL_3 0x03
276 #define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0
278 #define MIPI_LANE_CTRL_0 0x05
279 #define MIPI_TIME_HS_PRPR 0x08
285 #define MIPI_VIDEO_STABLE_CNT 0x0A
287 #define MIPI_LANE_CTRL_10 0x0F
288 #define MIPI_DIGITAL_ADJ_1 0x1B
289 #define IVO_MID 0x26CF
291 #define MIPI_PLL_M_NUM_23_16 0x1E
292 #define MIPI_PLL_M_NUM_15_8 0x1F
293 #define MIPI_PLL_M_NUM_7_0 0x20
294 #define MIPI_PLL_N_NUM_23_16 0x21
295 #define MIPI_PLL_N_NUM_15_8 0x22
296 #define MIPI_PLL_N_NUM_7_0 0x23
298 #define MIPI_DIGITAL_PLL_6 0x2A
300 #define MIPI_M_NUM_READY 0x10
301 #define MIPI_N_NUM_READY 0x08
302 #define STABLE_INTEGER_CNT_EN 0x04
303 #define MIPI_PLL_TEST_BIT 0
304 /* Bit[1:0]: test point output select - */
307 #define MIPI_DIGITAL_PLL_7 0x2B
314 #define MIPI_PLL_VCO_TUNE_REG_VAL 0x30
319 #define MIPI_PLL_RESET_N 0x02
320 #define MIPI_FRQ_FORCE_NDET 0
322 #define MIPI_ALERT_CLR_0 0x2D
324 /* This bit itself is S/C, and it clears 0x84:0x31[7] */
326 #define MIPI_ALERT_OUT_0 0x31
328 /* This bit is cleared by 0x84:0x2D[7] */
330 #define MIPI_DIGITAL_PLL_8 0x33
332 /* N means divided by (n+1), n = 0~15 */
336 /* Bit 0 is reserved */
338 #define MIPI_DIGITAL_PLL_9 0x34
340 #define MIPI_DIGITAL_PLL_16 0x3B
349 #define REF_CLK_19200KHZ 0
350 #define MIPI_REG_PLL_PLL_TEST_ENABLE 0
352 #define MIPI_DIGITAL_PLL_18 0x3D
357 #define SELECT_DPI 0
358 #define REG_BAUD_DIV_RATIO 0
360 #define H_BLANK_L 0x3E
362 #define H_BLANK_H 0x3F
364 #define MIPI_SWAP 0x4A
370 /* Bit[2:0] are reserved */
372 /******** END of I2C Address 0x84 *********/
375 #define DPCD_DPCD_REV 0x00
376 #define DPCD_MAX_LINK_RATE 0x01
377 #define DPCD_MAX_LANE_COUNT 0x02
383 AUDIO_FS_441K = 0x00,
384 AUDIO_FS_48K = 0x02,
385 AUDIO_FS_32K = 0x03,
386 AUDIO_FS_882K = 0x08,
387 AUDIO_FS_96K = 0x0a,
388 AUDIO_FS_1764K = 0x0c,
389 AUDIO_FS_192K = 0x0e
393 AUDIO_W_LEN_16_20MAX = 0x02,
394 AUDIO_W_LEN_18_20MAX = 0x04,
395 AUDIO_W_LEN_17_20MAX = 0x0c,
396 AUDIO_W_LEN_19_20MAX = 0x08,
397 AUDIO_W_LEN_20_20MAX = 0x0a,
398 AUDIO_W_LEN_20_24MAX = 0x03,
399 AUDIO_W_LEN_22_24MAX = 0x05,
400 AUDIO_W_LEN_21_24MAX = 0x0d,
401 AUDIO_W_LEN_23_24MAX = 0x09,
402 AUDIO_W_LEN_24_24MAX = 0x0b
405 #define I2S_CH_2 0x01
406 #define TDM_CH_4 0x03
407 #define TDM_CH_6 0x05
408 #define TDM_CH_8 0x07