Lines Matching refs:ast
37 static void ast_post_chip_2300(struct ast_device *ast);
38 static void ast_post_chip_2500(struct ast_device *ast);
43 static void ast_set_def_ext_reg(struct ast_device *ast) in ast_set_def_ext_reg() argument
50 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00); in ast_set_def_ext_reg()
52 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) in ast_set_def_ext_reg()
59 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
68 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
69 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
73 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) in ast_set_def_ext_reg()
75 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg); in ast_set_def_ext_reg()
106 u32 ast_mindwm(struct ast_device *ast, u32 r) in ast_mindwm() argument
108 return __ast_mindwm(ast->regs, r); in ast_mindwm()
111 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v) in ast_moutdwm() argument
113 __ast_moutdwm(ast->regs, r, v); in ast_moutdwm()
144 static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen) in mmctestburst2_ast2150() argument
148 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
149 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); in mmctestburst2_ast2150()
152 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
154 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
158 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
159 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); in mmctestburst2_ast2150()
162 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
164 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
168 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; in mmctestburst2_ast2150()
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
174 static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
178 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
182 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
184 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
188 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
189 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
194 static int cbrtest_ast2150(struct ast_device *ast) in cbrtest_ast2150() argument
199 if (mmctestburst2_ast2150(ast, i)) in cbrtest_ast2150()
204 static int cbrscan_ast2150(struct ast_device *ast, int busw) in cbrscan_ast2150() argument
209 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); in cbrscan_ast2150()
211 if (cbrtest_ast2150(ast)) in cbrscan_ast2150()
221 static void cbrdlli_ast2150(struct ast_device *ast, int busw) in cbrdlli_ast2150() argument
231 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
232 data = cbrscan_ast2150(ast, busw); in cbrdlli_ast2150()
248 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
253 static void ast_init_dram_reg(struct ast_device *ast) in ast_init_dram_reg() argument
259 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dram_reg()
262 if (IS_AST_GEN1(ast)) { in ast_init_dram_reg()
264 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
265 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
266 ast_write32(ast, 0x10100, 0xa8); in ast_init_dram_reg()
270 } while (ast_read32(ast, 0x10100) != 0xa8); in ast_init_dram_reg()
272 if (ast->chip == AST2100 || ast->chip == AST2200) in ast_init_dram_reg()
277 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
278 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
279 ast_write32(ast, 0x12000, 0x1688A8A8); in ast_init_dram_reg()
282 } while (ast_read32(ast, 0x12000) != 0x01); in ast_init_dram_reg()
284 ast_write32(ast, 0x10000, 0xfc600309); in ast_init_dram_reg()
287 } while (ast_read32(ast, 0x10000) != 0x01); in ast_init_dram_reg()
294 } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) { in ast_init_dram_reg()
296 if (ast->dram_type == AST_DRAM_1Gx16) in ast_init_dram_reg()
298 else if (ast->dram_type == AST_DRAM_1Gx32) in ast_init_dram_reg()
301 temp = ast_read32(ast, 0x12070); in ast_init_dram_reg()
304 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp); in ast_init_dram_reg()
306 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data); in ast_init_dram_reg()
311 data = ast_read32(ast, 0x10120); in ast_init_dram_reg()
313 data = ast_read32(ast, 0x10004); in ast_init_dram_reg()
315 cbrdlli_ast2150(ast, 16); /* 16 bits */ in ast_init_dram_reg()
317 cbrdlli_ast2150(ast, 32); /* 32 bits */ in ast_init_dram_reg()
320 switch (AST_GEN(ast)) { in ast_init_dram_reg()
322 temp = ast_read32(ast, 0x10140); in ast_init_dram_reg()
323 ast_write32(ast, 0x10140, temp | 0x40); in ast_init_dram_reg()
327 temp = ast_read32(ast, 0x1200c); in ast_init_dram_reg()
328 ast_write32(ast, 0x1200c, temp & 0xfffffffd); in ast_init_dram_reg()
329 temp = ast_read32(ast, 0x12040); in ast_init_dram_reg()
330 ast_write32(ast, 0x12040, temp | 0x40); in ast_init_dram_reg()
339 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dram_reg()
343 void ast_post_gpu(struct ast_device *ast) in ast_post_gpu() argument
345 ast_set_def_ext_reg(ast); in ast_post_gpu()
347 if (IS_AST_GEN7(ast)) { in ast_post_gpu()
348 if (ast->tx_chip == AST_TX_ASTDP) in ast_post_gpu()
349 ast_dp_launch(ast); in ast_post_gpu()
350 } else if (ast->config_mode == ast_use_p2a) { in ast_post_gpu()
351 if (IS_AST_GEN6(ast)) in ast_post_gpu()
352 ast_post_chip_2500(ast); in ast_post_gpu()
353 else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast)) in ast_post_gpu()
354 ast_post_chip_2300(ast); in ast_post_gpu()
356 ast_init_dram_reg(ast); in ast_post_gpu()
358 ast_init_3rdtx(ast); in ast_post_gpu()
360 if (ast->tx_chip == AST_TX_SIL164) in ast_post_gpu()
361 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); /* Enable DVO */ in ast_post_gpu()
418 static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl) in mmc_test() argument
422 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
423 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test()
426 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; in mmc_test()
430 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
434 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test()
438 static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl) in mmc_test2() argument
442 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
443 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test2()
446 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; in mmc_test2()
448 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test2()
452 data = ast_mindwm(ast, 0x1e6e0078); in mmc_test2()
454 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
459 static bool mmc_test_burst(struct ast_device *ast, u32 datagen) in mmc_test_burst() argument
461 return mmc_test(ast, datagen, 0xc1); in mmc_test_burst()
464 static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen) in mmc_test_burst2() argument
466 return mmc_test2(ast, datagen, 0x41); in mmc_test_burst2()
469 static bool mmc_test_single(struct ast_device *ast, u32 datagen) in mmc_test_single() argument
471 return mmc_test(ast, datagen, 0xc5); in mmc_test_single()
474 static u32 mmc_test_single2(struct ast_device *ast, u32 datagen) in mmc_test_single2() argument
476 return mmc_test2(ast, datagen, 0x05); in mmc_test_single2()
479 static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen) in mmc_test_single_2500() argument
481 return mmc_test(ast, datagen, 0x85); in mmc_test_single_2500()
484 static int cbr_test(struct ast_device *ast) in cbr_test() argument
488 data = mmc_test_single2(ast, 0); in cbr_test()
492 data = mmc_test_burst2(ast, i); in cbr_test()
503 static int cbr_scan(struct ast_device *ast) in cbr_scan() argument
509 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan()
511 if ((data = cbr_test(ast)) != 0) { in cbr_scan()
524 static u32 cbr_test2(struct ast_device *ast) in cbr_test2() argument
528 data = mmc_test_burst2(ast, 0); in cbr_test2()
531 data |= mmc_test_single2(ast, 0); in cbr_test2()
538 static u32 cbr_scan2(struct ast_device *ast) in cbr_scan2() argument
544 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan2()
546 if ((data = cbr_test2(ast)) != 0) { in cbr_scan2()
559 static bool cbr_test3(struct ast_device *ast) in cbr_test3() argument
561 if (!mmc_test_burst(ast, 0)) in cbr_test3()
563 if (!mmc_test_single(ast, 0)) in cbr_test3()
568 static bool cbr_scan3(struct ast_device *ast) in cbr_scan3() argument
573 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan3()
575 if (cbr_test3(ast)) in cbr_scan3()
584 static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param) in finetuneDQI_L() argument
595 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); in finetuneDQI_L()
596 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1); in finetuneDQI_L()
597 data = cbr_scan2(ast); in finetuneDQI_L()
654 ast_moutdwm(ast, 0x1E6E0080, data); in finetuneDQI_L()
679 ast_moutdwm(ast, 0x1E6E0084, data); in finetuneDQI_L()
683 static void finetuneDQSI(struct ast_device *ast) in finetuneDQSI() argument
692 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C); in finetuneDQSI()
693 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018); in finetuneDQSI()
695 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
710 ast_moutdwm(ast, 0x1E6E000C, 0); in finetuneDQSI()
711 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); in finetuneDQSI()
712 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c); in finetuneDQSI()
714 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in finetuneDQSI()
715 ast_moutdwm(ast, 0x1E6E0070, 0); in finetuneDQSI()
716 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0); in finetuneDQSI()
717 if (cbr_scan3(ast)) { in finetuneDQSI()
770 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
773 static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param) in cbr_dll2() argument
778 finetuneDQSI(ast); in cbr_dll2()
779 if (finetuneDQI_L(ast, param) == false) in cbr_dll2()
787 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in cbr_dll2()
788 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2); in cbr_dll2()
789 data = cbr_scan(ast); in cbr_dll2()
825 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16)); in cbr_dll2()
829 static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param) in get_ddr3_info() argument
833 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr3_info()
836 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr3_info()
850 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr3_info()
878 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr3_info()
908 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr3_info()
938 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr3_info()
952 ast_moutdwm(ast, 0x1E6E2020, 0x0270); in get_ddr3_info()
966 ast_moutdwm(ast, 0x1E6E2020, 0x0290); in get_ddr3_info()
982 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr3_info()
1000 ast_moutdwm(ast, 0x1E6E2020, 0x02E1); in get_ddr3_info()
1018 ast_moutdwm(ast, 0x1E6E2020, 0x0160); in get_ddr3_info()
1071 static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param) in ddr3_init() argument
1076 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr3_init()
1077 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr3_init()
1078 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr3_init()
1079 ast_moutdwm(ast, 0x1E6E0034, 0x00000000); in ddr3_init()
1081 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr3_init()
1082 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr3_init()
1084 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr3_init()
1087 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr3_init()
1088 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr3_init()
1089 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr3_init()
1090 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr3_init()
1091 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr3_init()
1092 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr3_init()
1093 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr3_init()
1094 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr3_init()
1095 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170); in ddr3_init()
1096 ast_moutdwm(ast, 0x1E6E0018, 0x00002370); in ddr3_init()
1097 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr3_init()
1098 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444); in ddr3_init()
1099 ast_moutdwm(ast, 0x1E6E0044, 0x22222222); in ddr3_init()
1100 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr3_init()
1101 ast_moutdwm(ast, 0x1E6E004C, 0x00000002); in ddr3_init()
1102 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1103 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1104 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr3_init()
1105 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr3_init()
1106 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr3_init()
1107 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1108 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr3_init()
1109 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr3_init()
1110 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1113 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1115 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1118 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr3_init()
1122 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr3_init()
1128 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr3_init()
1131 ast_moutdwm(ast, 0x1E6E0068, data); in ddr3_init()
1133 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr3_init()
1135 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr3_init()
1136 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1138 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1140 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1143 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1146 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff); in ddr3_init()
1147 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr3_init()
1148 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1150 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr3_init()
1151 ast_moutdwm(ast, 0x1E6E000C, 0x00000040); in ddr3_init()
1154 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr3_init()
1155 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr3_init()
1156 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr3_init()
1157 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr3_init()
1158 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr3_init()
1159 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1160 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr3_init()
1161 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr3_init()
1162 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1164 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr3_init()
1172 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr3_init()
1175 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) in ddr3_init()
1178 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr3_init()
1181 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1182 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr3_init()
1184 data = ast_mindwm(ast, 0x1E6E0070); in ddr3_init()
1186 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1187 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1188 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1194 static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param) in get_ddr2_info() argument
1198 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr2_info()
1201 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr2_info()
1215 ast_moutdwm(ast, 0x1E6E2020, 0x0130); in get_ddr2_info()
1230 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr2_info()
1261 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr2_info()
1295 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr2_info()
1328 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr2_info()
1343 ast_moutdwm(ast, 0x1E6E2020, 0x0261); in get_ddr2_info()
1359 ast_moutdwm(ast, 0x1E6E2020, 0x0120); in get_ddr2_info()
1375 ast_moutdwm(ast, 0x1E6E2020, 0x02A1); in get_ddr2_info()
1391 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr2_info()
1441 static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param) in ddr2_init() argument
1446 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr2_init()
1447 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr2_init()
1448 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr2_init()
1449 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr2_init()
1450 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr2_init()
1452 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr2_init()
1455 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr2_init()
1456 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr2_init()
1457 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr2_init()
1458 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr2_init()
1459 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr2_init()
1460 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr2_init()
1461 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr2_init()
1462 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr2_init()
1463 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130); in ddr2_init()
1464 ast_moutdwm(ast, 0x1E6E0018, 0x00002330); in ddr2_init()
1465 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr2_init()
1466 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000); in ddr2_init()
1467 ast_moutdwm(ast, 0x1E6E0044, 0x88848466); in ddr2_init()
1468 ast_moutdwm(ast, 0x1E6E0048, 0x44440008); in ddr2_init()
1469 ast_moutdwm(ast, 0x1E6E004C, 0x00000000); in ddr2_init()
1470 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1471 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1472 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr2_init()
1473 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr2_init()
1474 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr2_init()
1475 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1476 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr2_init()
1477 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr2_init()
1478 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1482 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1484 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1487 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr2_init()
1491 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr2_init()
1497 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr2_init()
1500 ast_moutdwm(ast, 0x1E6E0068, data); in ddr2_init()
1502 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr2_init()
1504 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr2_init()
1505 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1507 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1509 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1512 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1515 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff); in ddr2_init()
1516 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr2_init()
1517 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1519 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr2_init()
1520 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr2_init()
1523 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr2_init()
1524 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1525 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr2_init()
1526 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr2_init()
1527 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1528 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1530 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr2_init()
1531 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr2_init()
1532 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1533 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); in ddr2_init()
1534 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1535 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1536 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1538 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); in ddr2_init()
1546 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr2_init()
1547 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr2_init()
1550 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) in ddr2_init()
1555 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1556 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr2_init()
1558 data = ast_mindwm(ast, 0x1E6E0070); in ddr2_init()
1560 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1561 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1562 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1567 static void ast_post_chip_2300(struct ast_device *ast) in ast_post_chip_2300() argument
1573 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2300()
1575 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_post_chip_2300()
1576 ast_write32(ast, 0xf000, 0x1); in ast_post_chip_2300()
1577 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_post_chip_2300()
1580 } while (ast_read32(ast, 0x12000) != 0x1); in ast_post_chip_2300()
1582 ast_write32(ast, 0x10000, 0xfc600309); in ast_post_chip_2300()
1585 } while (ast_read32(ast, 0x10000) != 0x1); in ast_post_chip_2300()
1588 temp = ast_read32(ast, 0x12008); in ast_post_chip_2300()
1590 ast_write32(ast, 0x12008, temp); in ast_post_chip_2300()
1594 temp = ast_mindwm(ast, 0x1e6e2070); in ast_post_chip_2300()
1632 get_ddr3_info(ast, ¶m); in ast_post_chip_2300()
1633 ddr3_init(ast, ¶m); in ast_post_chip_2300()
1635 get_ddr2_info(ast, ¶m); in ast_post_chip_2300()
1636 ddr2_init(ast, ¶m); in ast_post_chip_2300()
1639 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2300()
1640 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2300()
1645 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2300()
1649 static bool cbr_test_2500(struct ast_device *ast) in cbr_test_2500() argument
1651 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in cbr_test_2500()
1652 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in cbr_test_2500()
1653 if (!mmc_test_burst(ast, 0)) in cbr_test_2500()
1655 if (!mmc_test_single_2500(ast, 0)) in cbr_test_2500()
1660 static bool ddr_test_2500(struct ast_device *ast) in ddr_test_2500() argument
1662 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in ddr_test_2500()
1663 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in ddr_test_2500()
1664 if (!mmc_test_burst(ast, 0)) in ddr_test_2500()
1666 if (!mmc_test_burst(ast, 1)) in ddr_test_2500()
1668 if (!mmc_test_burst(ast, 2)) in ddr_test_2500()
1670 if (!mmc_test_burst(ast, 3)) in ddr_test_2500()
1672 if (!mmc_test_single_2500(ast, 0)) in ddr_test_2500()
1677 static void ddr_init_common_2500(struct ast_device *ast) in ddr_init_common_2500() argument
1679 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in ddr_init_common_2500()
1680 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); in ddr_init_common_2500()
1681 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); in ddr_init_common_2500()
1682 ast_moutdwm(ast, 0x1E6E0040, 0x88448844); in ddr_init_common_2500()
1683 ast_moutdwm(ast, 0x1E6E0044, 0x24422288); in ddr_init_common_2500()
1684 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr_init_common_2500()
1685 ast_moutdwm(ast, 0x1E6E004C, 0x22222222); in ddr_init_common_2500()
1686 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr_init_common_2500()
1687 ast_moutdwm(ast, 0x1E6E0208, 0x00000000); in ddr_init_common_2500()
1688 ast_moutdwm(ast, 0x1E6E0218, 0x00000000); in ddr_init_common_2500()
1689 ast_moutdwm(ast, 0x1E6E0220, 0x00000000); in ddr_init_common_2500()
1690 ast_moutdwm(ast, 0x1E6E0228, 0x00000000); in ddr_init_common_2500()
1691 ast_moutdwm(ast, 0x1E6E0230, 0x00000000); in ddr_init_common_2500()
1692 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); in ddr_init_common_2500()
1693 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); in ddr_init_common_2500()
1694 ast_moutdwm(ast, 0x1E6E0240, 0x86000000); in ddr_init_common_2500()
1695 ast_moutdwm(ast, 0x1E6E0244, 0x00008600); in ddr_init_common_2500()
1696 ast_moutdwm(ast, 0x1E6E0248, 0x80000000); in ddr_init_common_2500()
1697 ast_moutdwm(ast, 0x1E6E024C, 0x80808080); in ddr_init_common_2500()
1700 static void ddr_phy_init_2500(struct ast_device *ast) in ddr_phy_init_2500() argument
1705 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1708 data = ast_mindwm(ast, 0x1E6E0060) & 0x1; in ddr_phy_init_2500()
1713 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; in ddr_phy_init_2500()
1718 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr_phy_init_2500()
1720 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1724 ast_moutdwm(ast, 0x1E6E0060, 0x00000006); in ddr_phy_init_2500()
1734 static void check_dram_size_2500(struct ast_device *ast, u32 tRFC) in check_dram_size_2500() argument
1738 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; in check_dram_size_2500()
1739 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; in check_dram_size_2500()
1741 ast_moutdwm(ast, 0xA0100000, 0x41424344); in check_dram_size_2500()
1742 ast_moutdwm(ast, 0x90100000, 0x35363738); in check_dram_size_2500()
1743 ast_moutdwm(ast, 0x88100000, 0x292A2B2C); in check_dram_size_2500()
1744 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); in check_dram_size_2500()
1747 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { in check_dram_size_2500()
1751 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { in check_dram_size_2500()
1755 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { in check_dram_size_2500()
1761 ast_moutdwm(ast, 0x1E6E0004, reg_04); in check_dram_size_2500()
1762 ast_moutdwm(ast, 0x1E6E0014, reg_14); in check_dram_size_2500()
1765 static void enable_cache_2500(struct ast_device *ast) in enable_cache_2500() argument
1769 reg_04 = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1770 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); in enable_cache_2500()
1773 data = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1775 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); in enable_cache_2500()
1778 static void set_mpll_2500(struct ast_device *ast) in set_mpll_2500() argument
1783 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in set_mpll_2500()
1784 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in set_mpll_2500()
1786 ast_moutdwm(ast, addr, 0x0); in set_mpll_2500()
1789 ast_moutdwm(ast, 0x1E6E0034, 0x00020000); in set_mpll_2500()
1791 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in set_mpll_2500()
1792 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; in set_mpll_2500()
1796 ast_moutdwm(ast, 0x1E6E2160, 0x00011320); in set_mpll_2500()
1801 ast_moutdwm(ast, 0x1E6E2020, param); in set_mpll_2500()
1805 static void reset_mmc_2500(struct ast_device *ast) in reset_mmc_2500() argument
1807 ast_moutdwm(ast, 0x1E78505C, 0x00000004); in reset_mmc_2500()
1808 ast_moutdwm(ast, 0x1E785044, 0x00000001); in reset_mmc_2500()
1809 ast_moutdwm(ast, 0x1E785048, 0x00004755); in reset_mmc_2500()
1810 ast_moutdwm(ast, 0x1E78504C, 0x00000013); in reset_mmc_2500()
1812 ast_moutdwm(ast, 0x1E785054, 0x00000077); in reset_mmc_2500()
1813 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in reset_mmc_2500()
1816 static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table) in ddr3_init_2500() argument
1819 ast_moutdwm(ast, 0x1E6E0004, 0x00000303); in ddr3_init_2500()
1820 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr3_init_2500()
1821 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr3_init_2500()
1822 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr3_init_2500()
1823 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr3_init_2500()
1824 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr3_init_2500()
1825 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr3_init_2500()
1826 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr3_init_2500()
1829 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); in ddr3_init_2500()
1830 ast_moutdwm(ast, 0x1E6E0204, 0x00001001); in ddr3_init_2500()
1831 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr3_init_2500()
1832 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr3_init_2500()
1833 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr3_init_2500()
1834 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr3_init_2500()
1835 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr3_init_2500()
1836 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr3_init_2500()
1837 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr3_init_2500()
1838 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr3_init_2500()
1839 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr3_init_2500()
1840 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr3_init_2500()
1841 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr3_init_2500()
1842 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); in ddr3_init_2500()
1845 ast_moutdwm(ast, 0x1E6E0034, 0x00020091); in ddr3_init_2500()
1848 ddr_phy_init_2500(ast); in ddr3_init_2500()
1850 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr3_init_2500()
1851 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr3_init_2500()
1852 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr3_init_2500()
1854 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); in ddr3_init_2500()
1855 enable_cache_2500(ast); in ddr3_init_2500()
1856 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr3_init_2500()
1857 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr3_init_2500()
1860 static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) in ddr4_init_2500() argument
1867 ast_moutdwm(ast, 0x1E6E0004, 0x00000313); in ddr4_init_2500()
1868 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr4_init_2500()
1869 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr4_init_2500()
1870 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr4_init_2500()
1871 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr4_init_2500()
1872 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr4_init_2500()
1873 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr4_init_2500()
1874 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr4_init_2500()
1877 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); in ddr4_init_2500()
1878 ast_moutdwm(ast, 0x1E6E0204, 0x09002000); in ddr4_init_2500()
1879 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr4_init_2500()
1880 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr4_init_2500()
1881 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr4_init_2500()
1882 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr4_init_2500()
1883 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr4_init_2500()
1884 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr4_init_2500()
1885 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr4_init_2500()
1886 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr4_init_2500()
1887 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr4_init_2500()
1888 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr4_init_2500()
1889 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr4_init_2500()
1890 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); in ddr4_init_2500()
1891 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); in ddr4_init_2500()
1894 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); in ddr4_init_2500()
1902 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); in ddr4_init_2500()
1904 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1905 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1906 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); in ddr4_init_2500()
1908 ddr_phy_init_2500(ast); in ddr4_init_2500()
1909 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1910 if (cbr_test_2500(ast)) { in ddr4_init_2500()
1912 data = ast_mindwm(ast, 0x1E6E03D0); in ddr4_init_2500()
1925 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); in ddr4_init_2500()
1935 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1936 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1937 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1939 ddr_phy_init_2500(ast); in ddr4_init_2500()
1940 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1941 if (cbr_test_2500(ast)) { in ddr4_init_2500()
1952 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1953 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1955 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1958 ddr_phy_init_2500(ast); in ddr4_init_2500()
1960 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr4_init_2500()
1961 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr4_init_2500()
1962 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr4_init_2500()
1964 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); in ddr4_init_2500()
1965 enable_cache_2500(ast); in ddr4_init_2500()
1966 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr4_init_2500()
1967 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr4_init_2500()
1970 static bool ast_dram_init_2500(struct ast_device *ast) in ast_dram_init_2500() argument
1978 set_mpll_2500(ast); in ast_dram_init_2500()
1979 reset_mmc_2500(ast); in ast_dram_init_2500()
1980 ddr_init_common_2500(ast); in ast_dram_init_2500()
1982 data = ast_mindwm(ast, 0x1E6E2070); in ast_dram_init_2500()
1984 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table); in ast_dram_init_2500()
1986 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table); in ast_dram_init_2500()
1987 } while (!ddr_test_2500(ast)); in ast_dram_init_2500()
1989 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); in ast_dram_init_2500()
1992 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; in ast_dram_init_2500()
1993 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); in ast_dram_init_2500()
2035 void ast_post_chip_2500(struct ast_device *ast) in ast_post_chip_2500() argument
2037 struct drm_device *dev = &ast->base; in ast_post_chip_2500()
2041 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2500()
2044 ast_patch_ahb_2500(ast->regs); in ast_post_chip_2500()
2047 ast_moutdwm(ast, 0x1E78502C, 0x00000000); in ast_post_chip_2500()
2048 ast_moutdwm(ast, 0x1E78504C, 0x00000000); in ast_post_chip_2500()
2063 ast_moutdwm(ast, 0x1E6E2090, 0x20000000); in ast_post_chip_2500()
2064 ast_moutdwm(ast, 0x1E6E2094, 0x00004000); in ast_post_chip_2500()
2065 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { in ast_post_chip_2500()
2066 ast_moutdwm(ast, 0x1E6E207C, 0x00800000); in ast_post_chip_2500()
2068 ast_moutdwm(ast, 0x1E6E2070, 0x00800000); in ast_post_chip_2500()
2071 temp = ast_mindwm(ast, 0x1E6E2070); in ast_post_chip_2500()
2073 ast_moutdwm(ast, 0x1E6E207C, 0x00004000); in ast_post_chip_2500()
2076 temp = ast_read32(ast, 0x12008); in ast_post_chip_2500()
2078 ast_write32(ast, 0x12008, temp); in ast_post_chip_2500()
2080 if (!ast_dram_init_2500(ast)) in ast_post_chip_2500()
2083 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2500()
2084 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2500()
2089 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2500()