1 // SPDX-License-Identifier: GPL-2.0+
4 #include <linux/clk.h>
28 	struct drm_crtc *crtc = &priv->pipe.crtc;  in aspeed_gfx_set_pixel_fmt()
29 	struct drm_device *drm = crtc->dev;  in aspeed_gfx_set_pixel_fmt()
30 	const u32 format = crtc->primary->state->fb->format->format;  in aspeed_gfx_set_pixel_fmt()
33 	ctrl1 = readl(priv->base + CRT_CTRL1);  in aspeed_gfx_set_pixel_fmt()
38 		dev_dbg(drm->dev, "Setting up RGB565 mode\n");  in aspeed_gfx_set_pixel_fmt()
43 		dev_dbg(drm->dev, "Setting up XRGB8888 mode\n");  in aspeed_gfx_set_pixel_fmt()
48 		dev_err(drm->dev, "Unhandled pixel format %08x\n", format);  in aspeed_gfx_set_pixel_fmt()
49 		return -EINVAL;  in aspeed_gfx_set_pixel_fmt()
52 	writel(ctrl1, priv->base + CRT_CTRL1);  in aspeed_gfx_set_pixel_fmt()
59 	u32 ctrl1 = readl(priv->base + CRT_CTRL1);  in aspeed_gfx_enable_controller()
60 	u32 ctrl2 = readl(priv->base + CRT_CTRL2);  in aspeed_gfx_enable_controller()
63 	regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), BIT(16));  in aspeed_gfx_enable_controller()
65 	writel(ctrl1 | CRT_CTRL_EN, priv->base + CRT_CTRL1);  in aspeed_gfx_enable_controller()
66 	writel(ctrl2 | CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2);  in aspeed_gfx_enable_controller()
71 	u32 ctrl1 = readl(priv->base + CRT_CTRL1);  in aspeed_gfx_disable_controller()
72 	u32 ctrl2 = readl(priv->base + CRT_CTRL2);  in aspeed_gfx_disable_controller()
74 	writel(ctrl1 & ~CRT_CTRL_EN, priv->base + CRT_CTRL1);  in aspeed_gfx_disable_controller()
75 	writel(ctrl2 & ~CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2);  in aspeed_gfx_disable_controller()
77 	regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0);  in aspeed_gfx_disable_controller()
82 	struct drm_display_mode *m = &priv->pipe.crtc.state->adjusted_mode;  in aspeed_gfx_crtc_mode_set_nofb()
93 	clk_set_rate(priv->pixel_clk, m->crtc_clock * 1000);  in aspeed_gfx_crtc_mode_set_nofb()
96 	ctrl1 = readl(priv->base + CRT_CTRL1);  in aspeed_gfx_crtc_mode_set_nofb()
101 	if (m->flags & DRM_MODE_FLAG_INTERLACE)  in aspeed_gfx_crtc_mode_set_nofb()
104 	if (!(m->flags & DRM_MODE_FLAG_PHSYNC))  in aspeed_gfx_crtc_mode_set_nofb()
107 	if (!(m->flags & DRM_MODE_FLAG_PVSYNC))  in aspeed_gfx_crtc_mode_set_nofb()
110 	writel(ctrl1, priv->base + CRT_CTRL1);  in aspeed_gfx_crtc_mode_set_nofb()
113 	writel(CRT_H_TOTAL(m->htotal - 1) | CRT_H_DE(m->hdisplay - 1),  in aspeed_gfx_crtc_mode_set_nofb()
114 			priv->base + CRT_HORIZ0);  in aspeed_gfx_crtc_mode_set_nofb()
115 	writel(CRT_H_RS_START(m->hsync_start - 1) | CRT_H_RS_END(m->hsync_end),  in aspeed_gfx_crtc_mode_set_nofb()
116 			priv->base + CRT_HORIZ1);  in aspeed_gfx_crtc_mode_set_nofb()
120 	writel(CRT_V_TOTAL(m->vtotal - 1) | CRT_V_DE(m->vdisplay - 1),  in aspeed_gfx_crtc_mode_set_nofb()
121 			priv->base + CRT_VERT0);  in aspeed_gfx_crtc_mode_set_nofb()
122 	writel(CRT_V_RS_START(m->vsync_start) | CRT_V_RS_END(m->vsync_end),  in aspeed_gfx_crtc_mode_set_nofb()
123 			priv->base + CRT_VERT1);  in aspeed_gfx_crtc_mode_set_nofb()
129 	d_offset = m->hdisplay * bpp / 8;  in aspeed_gfx_crtc_mode_set_nofb()
130 	t_count = DIV_ROUND_UP(m->hdisplay * bpp, priv->scan_line_max);  in aspeed_gfx_crtc_mode_set_nofb()
133 			priv->base + CRT_OFFSET);  in aspeed_gfx_crtc_mode_set_nofb()
139 	writel(priv->throd_val, priv->base + CRT_THROD);  in aspeed_gfx_crtc_mode_set_nofb()
147 	struct drm_crtc *crtc = &pipe->crtc;  in aspeed_gfx_pipe_enable()
157 	struct drm_crtc *crtc = &pipe->crtc;  in aspeed_gfx_pipe_disable()
167 	struct drm_crtc *crtc = &pipe->crtc;  in aspeed_gfx_pipe_update()
168 	struct drm_framebuffer *fb = pipe->plane.state->fb;  in aspeed_gfx_pipe_update()
172 	spin_lock_irq(&crtc->dev->event_lock);  in aspeed_gfx_pipe_update()
173 	event = crtc->state->event;  in aspeed_gfx_pipe_update()
175 		crtc->state->event = NULL;  in aspeed_gfx_pipe_update()
182 	spin_unlock_irq(&crtc->dev->event_lock);  in aspeed_gfx_pipe_update()
190 	writel(gem->dma_addr, priv->base + CRT_ADDR);  in aspeed_gfx_pipe_update()
196 	u32 reg = readl(priv->base + CRT_CTRL1);  in aspeed_gfx_enable_vblank()
199 	writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1);  in aspeed_gfx_enable_vblank()
202 	writel(reg, priv->base + CRT_CTRL1);  in aspeed_gfx_enable_vblank()
210 	u32 reg = readl(priv->base + CRT_CTRL1);  in aspeed_gfx_disable_vblank()
213 	writel(reg, priv->base + CRT_CTRL1);  in aspeed_gfx_disable_vblank()
216 	writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1);  in aspeed_gfx_disable_vblank()
236 	return drm_simple_display_pipe_init(drm, &priv->pipe, &aspeed_gfx_funcs,  in aspeed_gfx_create_pipe()
240 					    &priv->connector);  in aspeed_gfx_create_pipe()