Lines Matching full:hdlcd

9  *  ARM HDLCD Driver
44 	struct hdlcd_drm_private *hdlcd = arg;
47 	irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
51 		atomic_inc(&hdlcd->buffer_underrun_count);
54 		atomic_inc(&hdlcd->dma_end_count);
57 		atomic_inc(&hdlcd->bus_error_count);
60 		atomic_inc(&hdlcd->vsync_count);
64 		drm_crtc_handle_vblank(&hdlcd->crtc);
67 	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
72 static int hdlcd_irq_install(struct hdlcd_drm_private *hdlcd)
77 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
78 	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
80 	ret = request_irq(hdlcd->irq, hdlcd_irq, 0, "hdlcd", hdlcd);
86 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, HDLCD_DEBUG_INT_MASK);
92 static void hdlcd_irq_uninstall(struct hdlcd_drm_private *hdlcd)
95 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
97 	free_irq(hdlcd->irq, hdlcd);
102 	struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
107 	hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
108 	if (IS_ERR(hdlcd->clk))
109 		return PTR_ERR(hdlcd->clk);
112 	atomic_set(&hdlcd->buffer_underrun_count, 0);
113 	atomic_set(&hdlcd->bus_error_count, 0);
114 	atomic_set(&hdlcd->vsync_count, 0);
115 	atomic_set(&hdlcd->dma_end_count, 0);
118 	hdlcd->mmio = devm_platform_ioremap_resource(pdev, 0);
119 	if (IS_ERR(hdlcd->mmio)) {
121 		ret = PTR_ERR(hdlcd->mmio);
122 		hdlcd->mmio = NULL;
126 	version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
131 	DRM_INFO("found ARM HDLCD version r%dp%d\n",
153 	hdlcd->irq = ret;
155 	ret = hdlcd_irq_install(hdlcd);
164 	drm_crtc_cleanup(&hdlcd->crtc);
199 	struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
201 	seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
202 	seq_printf(m, "dma_end  : %d\n", atomic_read(&hdlcd->dma_end_count));
203 	seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
204 	seq_printf(m, "vsync    : %d\n", atomic_read(&hdlcd->vsync_count));
212 	struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
213 	unsigned long clkrate = clk_get_rate(hdlcd->clk);
214 	unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
234 	.name = "hdlcd",
235 	.desc = "ARM HDLCD Controller DRM",
243 	struct hdlcd_drm_private *hdlcd;
246 	hdlcd = devm_drm_dev_alloc(dev, &hdlcd_driver, typeof(*hdlcd), base);
247 	if (IS_ERR(hdlcd))
248 		return PTR_ERR(hdlcd);
250 	drm = &hdlcd->base;
263 	hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
287 	if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {
288 		hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
315 	of_node_put(hdlcd->crtc.port);
316 	hdlcd->crtc.port = NULL;
317 	hdlcd_irq_uninstall(hdlcd);
327 	struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
332 	of_node_put(hdlcd->crtc.port);
333 	hdlcd->crtc.port = NULL;
336 	hdlcd_irq_uninstall(hdlcd);
382 	{ .compatible	= "arm,hdlcd" },
410 		.name = "hdlcd",
419 MODULE_DESCRIPTION("ARM HDLCD DRM driver");