Lines Matching refs:ulv
5141 struct si_ulv_param *ulv = &si_pi->ulv;
5145 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5154 if (ulv->one_pcie_lane_in_ulv)
5170 struct si_ulv_param *ulv = &si_pi->ulv;
5174 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5180 ulv->volt_change_delay);
5204 const struct si_ulv_param *ulv = &si_pi->ulv;
5266 if (ulv->supported && ulv->pl.vddc) {
5275 WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control);
5276 WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5641 struct si_ulv_param *ulv = &si_pi->ulv;
5643 if (ulv->supported)
5654 const struct si_ulv_param *ulv = &si_pi->ulv;
5658 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5666 if (ulv->pl.vddc <
5682 const struct si_ulv_param *ulv = &si_pi->ulv;
5684 if (ulv->supported) {
5796 struct si_ulv_param *ulv = &si_pi->ulv;
5799 if (ulv->supported && ulv->pl.vddc) {
6149 struct si_ulv_param *ulv = &si_pi->ulv;
6166 if (ulv->supported && ulv->pl.vddc != 0)
6167 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
7241 si_pi->ulv.supported = false;
7242 si_pi->ulv.pl = *pl;
7243 si_pi->ulv.one_pcie_lane_in_ulv = false;
7244 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7245 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7246 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;