Lines Matching refs:dpm
105 rps == adev->pm.dpm.current_ps ? " c" : "",
106 rps == adev->pm.dpm.requested_ps ? " r" : "",
107 rps == adev->pm.dpm.boot_ps ? " b" : "");
117 for (i = 0; i < adev->pm.dpm.num_ps; i++)
118 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
146 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
147 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
148 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
216 adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
217 adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin);
218 adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed);
219 adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh);
220 adev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin);
221 adev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed);
222 adev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh);
224 adev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax);
226 adev->pm.dpm.fan.t_max = 10900;
227 adev->pm.dpm.fan.cycle_delay = 100000;
229 adev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode;
230 adev->pm.dpm.fan.default_max_fan_pwm =
232 adev->pm.dpm.fan.default_fan_output_sensitivity = 4836;
233 adev->pm.dpm.fan.fan_output_sensitivity =
236 adev->pm.dpm.fan.ucode_fan_control = true;
247 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
256 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
265 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
274 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
285 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk =
288 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk =
291 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc =
293 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci =
304 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
308 if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
313 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk =
315 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk =
317 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage =
322 adev->pm.dpm.dyn_state.phase_shedding_limits_table.count =
330 adev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
331 adev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
332 adev->pm.dpm.near_tdp_limit_adjusted = adev->pm.dpm.near_tdp_limit;
333 adev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
334 if (adev->pm.dpm.tdp_od_limit)
335 adev->pm.dpm.power_control = true;
337 adev->pm.dpm.power_control = false;
338 adev->pm.dpm.tdp_adjustment = 0;
339 adev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold);
340 adev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage);
341 adev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope);
349 adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);
350 if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries)
354 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
355 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 =
357 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 =
359 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 =
362 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
364 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
370 adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries;
401 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =
403 if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries)
405 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =
413 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk =
415 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk =
417 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
422 adev->pm.dpm.num_of_vce_states =
425 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
429 adev->pm.dpm.vce_states[i].evclk =
431 adev->pm.dpm.vce_states[i].ecclk =
433 adev->pm.dpm.vce_states[i].clk_idx =
435 adev->pm.dpm.vce_states[i].pstate =
454 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries =
456 if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries)
458 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count =
465 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk =
467 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
469 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
484 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries =
486 if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries)
488 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count =
492 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk =
494 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v =
505 adev->pm.dpm.dyn_state.ppm_table =
507 if (!adev->pm.dpm.dyn_state.ppm_table)
509 adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign;
510 adev->pm.dpm.dyn_state.ppm_table->cpu_core_number =
512 adev->pm.dpm.dyn_state.ppm_table->platform_tdp =
514 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp =
516 adev->pm.dpm.dyn_state.ppm_table->platform_tdc =
518 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc =
520 adev->pm.dpm.dyn_state.ppm_table->apu_tdp =
522 adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp =
524 adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power =
526 adev->pm.dpm.dyn_state.ppm_table->tj_max =
538 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries =
540 if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries)
542 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count =
546 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk =
548 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v =
559 adev->pm.dpm.dyn_state.cac_tdp_table =
561 if (!adev->pm.dpm.dyn_state.cac_tdp_table)
567 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
574 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255;
577 adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP);
578 adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp =
580 adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC);
581 adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit =
583 adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit =
585 adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage =
587 adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage =
596 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk,
608 struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state;
762 if (idx < adev->pm.dpm.num_of_vce_states)
763 return &adev->pm.dpm.vce_states[idx];
774 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
794 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
795 ps = &adev->pm.dpm.ps[i];
819 if (adev->pm.dpm.uvd_ps)
820 return adev->pm.dpm.uvd_ps;
840 return adev->pm.dpm.boot_ps;
869 if (adev->pm.dpm.uvd_ps) {
870 return adev->pm.dpm.uvd_ps;
901 /* if dpm init failed */
905 if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
907 if ((!adev->pm.dpm.thermal_active) &&
908 (!adev->pm.dpm.uvd_active))
909 adev->pm.dpm.state = adev->pm.dpm.user_state;
911 dpm_state = adev->pm.dpm.state;
915 adev->pm.dpm.requested_ps = ps;
921 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
923 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
927 ps->vce_active = adev->pm.dpm.vce_active;
936 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
948 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
949 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
952 if (adev->pm.dpm.thermal_active) {
953 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
957 adev->pm.dpm.forced_level = level;
960 pp_funcs->force_performance_level(adev, adev->pm.dpm.forced_level);
980 pm.dpm.thermal.work);
996 if (temp < adev->pm.dpm.thermal.min_temp)
998 dpm_state = adev->pm.dpm.user_state;
1000 if (adev->pm.dpm.thermal.high_to_low)
1002 dpm_state = adev->pm.dpm.user_state;
1006 adev->pm.dpm.thermal_active = true;
1008 adev->pm.dpm.thermal_active = false;
1010 adev->pm.dpm.state = dpm_state;