Lines Matching +full:auto +full:- +full:pm
33 #include <linux/hwmon-sysfs.h>
101 * amdgpu_pm_dev_state_check - Check if device can be accessed.
110 bool runpm_check = runpm ? adev->in_runpm : false; in amdgpu_pm_dev_state_check()
113 return -EBUSY; in amdgpu_pm_dev_state_check()
115 if (adev->in_suspend && !runpm_check) in amdgpu_pm_dev_state_check()
116 return -EBUSY; in amdgpu_pm_dev_state_check()
122 * amdgpu_pm_get_access - Check if device can be accessed, resume if needed.
125 * Checks the state of the @adev for access. Use runtime pm API to resume if
137 return pm_runtime_resume_and_get(adev->dev); in amdgpu_pm_get_access()
141 * amdgpu_pm_get_access_if_active - Check if device is active for access.
144 * Checks the state of the @adev for access. Use runtime pm API to determine
161 ret = pm_runtime_get_if_active(adev->dev); in amdgpu_pm_get_access_if_active()
163 return -EPERM; in amdgpu_pm_get_access_if_active()
169 * amdgpu_pm_put_access - Put to auto suspend mode after a device access.
176 pm_runtime_mark_last_busy(adev->dev); in amdgpu_pm_put_access()
177 pm_runtime_put_autosuspend(adev->dev); in amdgpu_pm_put_access()
188 * - battery
190 * - balanced
192 * - performance
220 enum amd_pm_state_type pm; in amdgpu_get_power_dpm_state() local
227 amdgpu_dpm_get_current_power_state(adev, &pm); in amdgpu_get_power_dpm_state()
232 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : in amdgpu_get_power_dpm_state()
233 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); in amdgpu_get_power_dpm_state()
253 return -EINVAL; in amdgpu_set_power_dpm_state()
274 * - auto
276 * - low
278 * - high
280 * - manual
282 * - profile_standard
284 * - profile_min_sclk
286 * - profile_min_mclk
288 * - profile_peak
290 * auto
292 * When auto is selected, the driver will attempt to dynamically select
344 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : in amdgpu_get_power_dpm_force_performance_level()
370 } else if (strncmp("auto", buf, strlen("auto")) == 0) { in amdgpu_set_power_dpm_force_performance_level()
387 return -EINVAL; in amdgpu_set_power_dpm_force_performance_level()
394 mutex_lock(&adev->pm.stable_pstate_ctx_lock); in amdgpu_set_power_dpm_force_performance_level()
397 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); in amdgpu_set_power_dpm_force_performance_level()
398 return -EINVAL; in amdgpu_set_power_dpm_force_performance_level()
401 adev->pm.stable_pstate_ctx = NULL; in amdgpu_set_power_dpm_force_performance_level()
402 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); in amdgpu_set_power_dpm_force_performance_level()
446 enum amd_pm_state_type pm = 0; in amdgpu_get_pp_cur_state() local
453 amdgpu_dpm_get_current_power_state(adev, &pm); in amdgpu_get_pp_cur_state()
463 if (pm == data.states[i]) in amdgpu_get_pp_cur_state()
468 i = -EINVAL; in amdgpu_get_pp_cur_state()
480 if (adev->pm.pp_force_state_enabled) in amdgpu_get_pp_force_state()
498 adev->pm.pp_force_state_enabled = false; in amdgpu_set_pp_force_state()
505 return -EINVAL; in amdgpu_set_pp_force_state()
527 adev->pm.pp_force_state_enabled = true; in amdgpu_set_pp_force_state()
546 * will attempt to upload a new powerplay table and re-initialize
572 size = PAGE_SIZE - 1; in amdgpu_get_pp_table()
659 * - a list of engine clock levels and voltages labeled OD_SCLK
661 * - a list of memory clock levels and voltages labeled OD_MCLK
663 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
679 * - minimum and maximum engine clock labeled OD_SCLK
681 * - minimum(not available for Vega20 and Navi1x) and maximum memory
684 * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
688 * - voltage offset(in mV) applied on target voltage calculation.
694 * - a list of valid ranges for sclk, mclk, voltage curve points
701 * - minimum and maximum engine clock labeled OD_SCLK
703 * - a list of valid ranges for sclk labeled OD_RANGE
709 * - minimum and maximum engine clock labeled OD_SCLK
710 * - minimum and maximum core clocks labeled OD_CCLK
712 * - a list of valid ranges for sclk and cclk labeled OD_RANGE
716 * - First select manual using power_dpm_force_performance_level
718 * - For clock frequency setting, enter a new value by writing a
736 * string that contains "vo offset". E.g., "vo -10" will update the extra
737 * voltage offset applied to the whole v/f curve line as -10mv.
739 * - When you have edited all of the states as needed, write "c" (commit)
742 * - If you want to reset to the default power levels, write "r" (reset)
764 return -EINVAL; in amdgpu_set_pp_od_clk_voltage()
781 return -EINVAL; in amdgpu_set_pp_od_clk_voltage()
798 return -EINVAL; in amdgpu_set_pp_od_clk_voltage()
836 return -EINVAL; in amdgpu_set_pp_od_clk_voltage()
866 if (ret == -ENOENT) { in amdgpu_get_pp_od_clk_voltage()
891 * - Current ppfeature masks
892 * - List of the all supported powerplay features with their naming,
911 return -EINVAL; in amdgpu_set_pp_features()
922 return -EINVAL; in amdgpu_set_pp_features()
979 * .. code-block:: bash
1002 if (ret == -ENOENT) in amdgpu_get_pp_dpm_clock()
1031 bytes = min(count, sizeof(buf_cpy) - 1); in amdgpu_read_mask()
1039 return -EINVAL; in amdgpu_read_mask()
1071 return -EINVAL; in amdgpu_set_pp_dpm_clock()
1259 return -EINVAL; in amdgpu_set_pp_sclk_od()
1305 return -EINVAL; in amdgpu_set_pp_mclk_od()
1386 return -EINVAL; in amdgpu_set_pp_power_profile_mode()
1390 return -EINVAL; in amdgpu_set_pp_power_profile_mode()
1393 memcpy(buf_cpy, buf, count-i); in amdgpu_set_pp_power_profile_mode()
1400 return -EINVAL; in amdgpu_set_pp_power_profile_mode()
1421 return -EINVAL; in amdgpu_set_pp_power_profile_mode()
1535 if (adev->flags & AMD_IS_APU) in amdgpu_get_pcie_bw()
1536 return -ENODATA; in amdgpu_get_pcie_bw()
1538 if (!adev->asic_funcs->get_pcie_usage) in amdgpu_get_pcie_bw()
1539 return -ENODATA; in amdgpu_get_pcie_bw()
1550 count0, count1, pcie_get_mps(adev->pdev)); in amdgpu_get_pcie_bw()
1570 if (adev->unique_id) in amdgpu_get_unique_id()
1571 return sysfs_emit(buf, "%016llx\n", adev->unique_id); in amdgpu_get_unique_id()
1599 adev_to_drm(adev)->unique, in amdgpu_get_thermal_throttling_logging()
1600 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", in amdgpu_get_thermal_throttling_logging()
1601 adev->throttling_logging_rs.interval / HZ + 1); in amdgpu_get_thermal_throttling_logging()
1619 return -EINVAL; in amdgpu_set_thermal_throttling_logging()
1626 ratelimit_state_reset_interval(&adev->throttling_logging_rs, in amdgpu_set_thermal_throttling_logging()
1627 (throttling_logging_interval - 1) * HZ); in amdgpu_set_thermal_throttling_logging()
1628 atomic_set(&adev->throttling_logging_enabled, 1); in amdgpu_set_thermal_throttling_logging()
1630 atomic_set(&adev->throttling_logging_enabled, 0); in amdgpu_set_thermal_throttling_logging()
1688 return -EINVAL; in amdgpu_set_apu_thermal_cap()
1712 if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP) in amdgpu_pm_metrics_attr_update()
1768 size = PAGE_SIZE - 1; in amdgpu_get_gpu_metrics()
1787 if (r == -EOPNOTSUPP) { in amdgpu_show_powershift_percent()
1792 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) { in amdgpu_show_powershift_percent()
1813 * there is no powershift and values between [1-100] means that the power
1829 * there is no powershift and values between [1-100] means that the power is
1844 * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1845 * and the default is 0. -100 sets maximum preference to APU
1940 if (!(attr->flags & mask)) in pp_od_clk_voltage_attr_update()
1949 struct device_attribute *dev_attr = &attr->dev_attr; in pp_dpm_dcefclk_attr_update()
1954 if (!(attr->flags & mask)) { in pp_dpm_dcefclk_attr_update()
1971 dev_attr->attr.mode &= ~S_IWUGO; in pp_dpm_dcefclk_attr_update()
1972 dev_attr->store = NULL; in pp_dpm_dcefclk_attr_update()
1981 struct device_attribute *dev_attr = &attr->dev_attr; in pp_dpm_clk_default_attr_update()
1982 enum amdgpu_device_attr_id attr_id = attr->attr_id; in pp_dpm_clk_default_attr_update()
1988 if (!(attr->flags & mask)) { in pp_dpm_clk_default_attr_update()
2020 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) in pp_dpm_clk_default_attr_update()
2043 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) in pp_dpm_clk_default_attr_update()
2060 dev_attr->attr.mode &= ~S_IWUGO; in pp_dpm_clk_default_attr_update()
2061 dev_attr->store = NULL; in pp_dpm_clk_default_attr_update()
2070 dev_attr->attr.mode &= ~S_IWUGO; in pp_dpm_clk_default_attr_update()
2071 dev_attr->store = NULL; in pp_dpm_clk_default_attr_update()
2088 * * .. code-block:: console
2128 ret = -ENOSPC; in amdgpu_get_baseboard_temp_metrics()
2166 ret = -ENOSPC; in amdgpu_get_gpuboard_temp_metrics()
2327 return attr->mode; in amdgpu_board_attr_visible()
2336 /* pm policy attributes */
2347 * per-process level. This is useful especially when entire SOC is utilized for
2353 * Pstate Policy Selection - This is to select different Pstate profiles which
2356 * XGMI PLPD Policy Selection - When multiple devices are connected over XGMI,
2369 * .. code-block:: console
2387 * XGMI and "soc_pstate_2" for soc pstate policy -
2389 * .. code-block:: console
2406 return amdgpu_dpm_get_pm_policy_info(adev, policy_attr->id, buf); in amdgpu_get_pm_policy_attr()
2424 tmp_buf[count - 1] = '\0'; in amdgpu_set_pm_policy_attr()
2435 return -EINVAL; in amdgpu_set_pm_policy_attr()
2438 return -EINVAL; in amdgpu_set_pm_policy_attr()
2442 return -EINVAL; in amdgpu_set_pm_policy_attr()
2451 ret = amdgpu_dpm_set_pm_policy(adev, policy_attr->id, val); in amdgpu_set_pm_policy_attr()
2490 if (amdgpu_dpm_get_pm_policy_info(adev, policy_attr->id, NULL) == in amdgpu_pm_policy_attr_visible()
2491 -ENOENT) in amdgpu_pm_policy_attr_visible()
2494 return attr->mode; in amdgpu_pm_policy_attr_visible()
2557 struct device_attribute *dev_attr = &attr->dev_attr; in default_attr_update()
2558 enum amdgpu_device_attr_id attr_id = attr->attr_id; in default_attr_update()
2561 if (!(attr->flags & mask)) { in default_attr_update()
2567 if ((adev->flags & AMD_IS_APU && in default_attr_update()
2591 if (adev->flags & AMD_IS_APU || in default_attr_update()
2592 !adev->asic_funcs->get_pcie_usage) in default_attr_update()
2616 if ((adev->flags & AMD_IS_APU && in default_attr_update()
2624 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) in default_attr_update()
2630 if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP) in default_attr_update()
2633 if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP) in default_attr_update()
2639 -EOPNOTSUPP) in default_attr_update()
2647 dev_attr->attr.mode &= ~0222; in default_attr_update()
2648 dev_attr->store = NULL; in default_attr_update()
2673 return -EINVAL; in amdgpu_device_attr_create()
2675 dev_attr = &attr->dev_attr; in amdgpu_device_attr_create()
2676 name = dev_attr->attr.name; in amdgpu_device_attr_create()
2678 attr_update = attr->attr_update ? attr->attr_update : default_attr_update; in amdgpu_device_attr_create()
2682 dev_err(adev->dev, "failed to update device file %s, ret = %d\n", in amdgpu_device_attr_create()
2690 ret = device_create_file(adev->dev, dev_attr); in amdgpu_device_attr_create()
2692 dev_err(adev->dev, "failed to create device file %s, ret = %d\n", in amdgpu_device_attr_create()
2698 return -ENOMEM; in amdgpu_device_attr_create()
2700 attr_entry->attr = attr; in amdgpu_device_attr_create()
2701 INIT_LIST_HEAD(&attr_entry->entry); in amdgpu_device_attr_create()
2703 list_add_tail(&attr_entry->entry, attr_list); in amdgpu_device_attr_create()
2710 struct device_attribute *dev_attr = &attr->dev_attr; in amdgpu_device_attr_remove()
2712 device_remove_file(adev->dev, dev_attr); in amdgpu_device_attr_remove()
2750 amdgpu_device_attr_remove(adev, entry->attr); in amdgpu_device_attr_remove_groups()
2751 list_del(&entry->entry); in amdgpu_device_attr_remove_groups()
2761 int channel = to_sensor_dev_attr(attr)->index; in amdgpu_hwmon_show_temp()
2765 return -EINVAL; in amdgpu_hwmon_show_temp()
2784 r = -EINVAL; in amdgpu_hwmon_show_temp()
2799 int hyst = to_sensor_dev_attr(attr)->index; in amdgpu_hwmon_show_temp_thresh()
2803 temp = adev->pm.dpm.thermal.min_temp; in amdgpu_hwmon_show_temp_thresh()
2805 temp = adev->pm.dpm.thermal.max_temp; in amdgpu_hwmon_show_temp_thresh()
2815 int hyst = to_sensor_dev_attr(attr)->index; in amdgpu_hwmon_show_hotspot_temp_thresh()
2819 temp = adev->pm.dpm.thermal.min_hotspot_temp; in amdgpu_hwmon_show_hotspot_temp_thresh()
2821 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; in amdgpu_hwmon_show_hotspot_temp_thresh()
2831 int hyst = to_sensor_dev_attr(attr)->index; in amdgpu_hwmon_show_mem_temp_thresh()
2835 temp = adev->pm.dpm.thermal.min_mem_temp; in amdgpu_hwmon_show_mem_temp_thresh()
2837 temp = adev->pm.dpm.thermal.max_mem_crit_temp; in amdgpu_hwmon_show_mem_temp_thresh()
2846 int channel = to_sensor_dev_attr(attr)->index; in amdgpu_hwmon_show_temp_label()
2849 return -EINVAL; in amdgpu_hwmon_show_temp_label()
2859 int channel = to_sensor_dev_attr(attr)->index; in amdgpu_hwmon_show_temp_emergency()
2863 return -EINVAL; in amdgpu_hwmon_show_temp_emergency()
2867 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; in amdgpu_hwmon_show_temp_emergency()
2870 temp = adev->pm.dpm.thermal.max_edge_emergency_temp; in amdgpu_hwmon_show_temp_emergency()
2873 temp = adev->pm.dpm.thermal.max_mem_emergency_temp; in amdgpu_hwmon_show_temp_emergency()
2897 return -EINVAL; in amdgpu_hwmon_get_pwm1_enable()
2923 return -EINVAL; in amdgpu_hwmon_set_pwm1_enable()
2934 return -EINVAL; in amdgpu_hwmon_set_pwm1_enable()
2976 err = -EINVAL; in amdgpu_hwmon_set_pwm1()
3113 err = -ENODATA; in amdgpu_hwmon_set_fan1_target()
3145 return -EINVAL; in amdgpu_hwmon_get_fan1_enable()
3169 return -EINVAL; in amdgpu_hwmon_set_fan1_enable()
3180 return -EINVAL; in amdgpu_hwmon_set_fan1_enable()
3241 if (!(adev->flags & AMD_IS_APU)) in amdgpu_hwmon_show_vddnb()
3242 return -EINVAL; in amdgpu_hwmon_show_vddnb()
3310 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; in amdgpu_hwmon_show_power_cap_generic()
3372 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? in amdgpu_hwmon_show_power_label()
3384 int limit_type = to_sensor_dev_attr(attr)->index; in amdgpu_hwmon_set_power_cap()
3462 * - GPU temperature (via the on-die sensor)
3464 * - GPU voltage
3466 * - Northbridge voltage (APUs only)
3468 * - GPU power
3470 * - GPU fan
3472 * - GPU gfx/compute engine clock
3474 * - GPU memory clock (dGPU only)
3478 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3479 * - temp2_input and temp3_input are supported on SOC15 dGPUs only
3481 * - temp[1-3]_label: temperature channel label
3482 * - temp2_label and temp3_label are supported on SOC15 dGPUs only
3484 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3485 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3487 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3488 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3490 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3491 * - these are supported on SOC15 dGPUs only
3495 * - in0_input: the voltage on the GPU in millivolts
3497 * - in1_input: the voltage on the Northbridge in millivolts
3501 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU.
3503 …* - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CP…
3505 * - power1_cap_min: minimum cap supported in microWatts
3507 * - power1_cap_max: maximum cap supported in microWatts
3509 * - power1_cap: selected power cap in microWatts
3513 * - pwm1: pulse width modulation fan level (0-255)
3515 …* - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan…
3517 * - pwm1_min: pulse width modulation fan control minimum level (0)
3519 * - pwm1_max: pulse width modulation fan control maximum level (255)
3521 * - fan1_min: a minimum value Unit: revolution/min (RPM)
3523 * - fan1_max: a maximum value Unit: revolution/max (RPM)
3525 * - fan1_input: fan speed in RPM
3527 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3529 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3531 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3536 * - freq1_input: the gfx/compute clock in hertz
3538 * - freq2_input: the memory clock in hertz
3648 umode_t effective_mode = attr->mode; in hwmon_attributes_visible()
3657 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || in hwmon_attributes_visible()
3669 if ((adev->flags & AMD_IS_APU) && in hwmon_attributes_visible()
3682 if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) || in hwmon_attributes_visible()
3690 if (!adev->pm.dpm_enabled && in hwmon_attributes_visible()
3705 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && in hwmon_attributes_visible()
3707 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && in hwmon_attributes_visible()
3711 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && in hwmon_attributes_visible()
3713 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && in hwmon_attributes_visible()
3722 if (adev->family == AMDGPU_FAMILY_SI || in hwmon_attributes_visible()
3723 ((adev->flags & AMD_IS_APU) && gc_ver != IP_VERSION(10, 3, 1) && in hwmon_attributes_visible()
3730 amdgpu_virt_cap_is_rw(&adev->virt.virt_caps, AMDGPU_VIRT_CAP_POWER_LIMIT)) in hwmon_attributes_visible()
3734 if (((adev->family == AMDGPU_FAMILY_SI) || in hwmon_attributes_visible()
3735 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && in hwmon_attributes_visible()
3742 (void *)&tmp) == -EOPNOTSUPP) in hwmon_attributes_visible()
3746 (void *)&tmp) == -EOPNOTSUPP) in hwmon_attributes_visible()
3750 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && in hwmon_attributes_visible()
3751 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && in hwmon_attributes_visible()
3752 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && in hwmon_attributes_visible()
3753 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && in hwmon_attributes_visible()
3758 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && in hwmon_attributes_visible()
3759 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && in hwmon_attributes_visible()
3764 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ in hwmon_attributes_visible()
3765 adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */ in hwmon_attributes_visible()
3774 if ((!(adev->flags & AMD_IS_APU) || in hwmon_attributes_visible()
3786 (void *)&tmp) == -EOPNOTSUPP) in hwmon_attributes_visible()
3790 if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) && in hwmon_attributes_visible()
3795 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && in hwmon_attributes_visible()
3816 return attr->mode; in hwmon_attributes_visible()
3820 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && in hwmon_attributes_visible()
3883 if (count > sizeof(buf_cpy) - 1) in parse_input_od_command_lines()
3884 return -EINVAL; in parse_input_od_command_lines()
3912 return -EINVAL; in parse_input_od_command_lines()
3994 * There are two fan control modes supported: auto and manual. With auto mode,
3997 * described here. Normally the ASIC is booted up with auto mode. Any
4006 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_curve_show()
4017 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_curve_store()
4029 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE) in fan_curve_visible()
4032 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET) in fan_curve_visible()
4055 * This setting works under auto fan control mode only. It adjusts the PMFW's
4057 * interface will switch the fan control to auto mode implicitly.
4064 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in acoustic_limit_threshold_show()
4075 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in acoustic_limit_threshold_store()
4087 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE) in acoustic_limit_threshold_visible()
4090 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET) in acoustic_limit_threshold_visible()
4113 * This setting works under auto fan control mode only. It can co-exist with
4114 * other settings which can work also under auto mode. It adjusts the PMFW's
4117 * interface will switch the fan control to auto mode implicitly.
4124 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in acoustic_target_threshold_show()
4135 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in acoustic_target_threshold_store()
4147 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE) in acoustic_target_threshold_visible()
4150 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET) in acoustic_target_threshold_visible()
4173 * This setting works under auto fan control mode only. It can co-exist with
4174 * other settings which can work also under auto mode. Paring with the
4178 * auto mode implicitly.
4185 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_target_temperature_show()
4196 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_target_temperature_store()
4208 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE) in fan_target_temperature_visible()
4211 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET) in fan_target_temperature_visible()
4234 * This setting works under auto fan control mode only. It can co-exist with
4235 * other settings which can work also under auto mode. It adjusts the PMFW's
4237 * via this interface will switch the fan control to auto mode implicitly.
4244 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_minimum_pwm_show()
4255 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_minimum_pwm_store()
4267 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE) in fan_minimum_pwm_visible()
4270 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET) in fan_minimum_pwm_visible()
4298 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_zero_rpm_enable_show()
4309 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_zero_rpm_enable_store()
4321 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE) in fan_zero_rpm_enable_visible()
4324 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET) in fan_zero_rpm_enable_visible()
4355 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_zero_rpm_stop_temp_show()
4366 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; in fan_zero_rpm_stop_temp_store()
4378 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE) in fan_zero_rpm_stop_temp_visible()
4381 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET) in fan_zero_rpm_stop_temp_visible()
4470 if (list_empty(&adev->pm.od_kobj_list)) in amdgpu_od_set_fini()
4474 &adev->pm.od_kobj_list, entry) { in amdgpu_od_set_fini()
4475 list_del(&container->entry); in amdgpu_od_set_fini()
4478 &container->attribute, entry) { in amdgpu_od_set_fini()
4479 list_del(&attribute->entry); in amdgpu_od_set_fini()
4480 sysfs_remove_file(&container->kobj, in amdgpu_od_set_fini()
4481 &attribute->attribute.attr); in amdgpu_od_set_fini()
4485 kobject_put(&container->kobj); in amdgpu_od_set_fini()
4494 if (!feature_ops->is_visible) in amdgpu_is_od_feature_supported()
4502 mode = feature_ops->is_visible(adev); in amdgpu_is_od_feature_supported()
4520 for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) { in amdgpu_od_is_self_contained()
4521 if (container->sub_feature[i].name && in amdgpu_od_is_self_contained()
4523 &container->sub_feature[i].ops)) in amdgpu_od_is_self_contained()
4542 return -ENOMEM; in amdgpu_od_set_init()
4543 list_add(&top_set->entry, &adev->pm.od_kobj_list); in amdgpu_od_set_init()
4545 ret = kobject_init_and_add(&top_set->kobj, in amdgpu_od_set_init()
4547 &adev->dev->kobj, in amdgpu_od_set_init()
4552 INIT_LIST_HEAD(&top_set->attribute); in amdgpu_od_set_init()
4553 top_set->priv = adev; in amdgpu_od_set_init()
4558 if (!container->name) in amdgpu_od_set_init()
4570 &container->ops)) in amdgpu_od_set_init()
4579 ret = -ENOMEM; in amdgpu_od_set_init()
4582 list_add(&attribute->entry, &top_set->attribute); in amdgpu_od_set_init()
4584 attribute->attribute.attr.mode = in amdgpu_od_set_init()
4585 container->ops.is_visible(adev); in amdgpu_od_set_init()
4586 attribute->attribute.attr.name = container->name; in amdgpu_od_set_init()
4587 attribute->attribute.show = in amdgpu_od_set_init()
4588 container->ops.show; in amdgpu_od_set_init()
4589 attribute->attribute.store = in amdgpu_od_set_init()
4590 container->ops.store; in amdgpu_od_set_init()
4591 ret = sysfs_create_file(&top_set->kobj, in amdgpu_od_set_init()
4592 &attribute->attribute.attr); in amdgpu_od_set_init()
4599 ret = -ENOMEM; in amdgpu_od_set_init()
4602 list_add(&sub_set->entry, &adev->pm.od_kobj_list); in amdgpu_od_set_init()
4604 ret = kobject_init_and_add(&sub_set->kobj, in amdgpu_od_set_init()
4606 &top_set->kobj, in amdgpu_od_set_init()
4608 container->name); in amdgpu_od_set_init()
4611 INIT_LIST_HEAD(&sub_set->attribute); in amdgpu_od_set_init()
4612 sub_set->priv = adev; in amdgpu_od_set_init()
4614 for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) { in amdgpu_od_set_init()
4615 feature = &container->sub_feature[j]; in amdgpu_od_set_init()
4616 if (!feature->name) in amdgpu_od_set_init()
4620 &feature->ops)) in amdgpu_od_set_init()
4629 ret = -ENOMEM; in amdgpu_od_set_init()
4632 list_add(&attribute->entry, &sub_set->attribute); in amdgpu_od_set_init()
4634 attribute->attribute.attr.mode = in amdgpu_od_set_init()
4635 feature->ops.is_visible(adev); in amdgpu_od_set_init()
4636 attribute->attribute.attr.name = feature->name; in amdgpu_od_set_init()
4637 attribute->attribute.show = in amdgpu_od_set_init()
4638 feature->ops.show; in amdgpu_od_set_init()
4639 attribute->attribute.store = in amdgpu_od_set_init()
4640 feature->ops.store; in amdgpu_od_set_init()
4641 ret = sysfs_create_file(&sub_set->kobj, in amdgpu_od_set_init()
4642 &attribute->attribute.attr); in amdgpu_od_set_init()
4653 if (list_is_singular(&adev->pm.od_kobj_list)) in amdgpu_od_set_init()
4671 if (adev->pm.sysfs_initialized) in amdgpu_pm_sysfs_init()
4674 INIT_LIST_HEAD(&adev->pm.pm_attr_list); in amdgpu_pm_sysfs_init()
4676 if (adev->pm.dpm_enabled == 0) in amdgpu_pm_sysfs_init()
4681 /* under multi-vf mode, the hwmon attributes are all not supported */ in amdgpu_pm_sysfs_init()
4683 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, in amdgpu_pm_sysfs_init()
4686 if (IS_ERR(adev->pm.int_hwmon_dev)) { in amdgpu_pm_sysfs_init()
4687 ret = PTR_ERR(adev->pm.int_hwmon_dev); in amdgpu_pm_sysfs_init()
4688 dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret); in amdgpu_pm_sysfs_init()
4710 &adev->pm.pm_attr_list); in amdgpu_pm_sysfs_init()
4718 } else if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) { in amdgpu_pm_sysfs_init()
4719 dev_info(adev->dev, "overdrive feature is not supported\n"); in amdgpu_pm_sysfs_init()
4723 -EOPNOTSUPP) { in amdgpu_pm_sysfs_init()
4724 ret = devm_device_add_group(adev->dev, in amdgpu_pm_sysfs_init()
4731 ret = devm_device_add_group(adev->dev, in amdgpu_pm_sysfs_init()
4736 (void *)&tmp) != -EOPNOTSUPP) { in amdgpu_pm_sysfs_init()
4737 sysfs_add_file_to_group(&adev->dev->kobj, in amdgpu_pm_sysfs_init()
4740 sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_node_power.attr, in amdgpu_pm_sysfs_init()
4742 sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_global_ppt_resid.attr, in amdgpu_pm_sysfs_init()
4744 sysfs_add_file_to_group(&adev->dev->kobj, in amdgpu_pm_sysfs_init()
4747 sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_npm_status.attr, in amdgpu_pm_sysfs_init()
4752 adev->pm.sysfs_initialized = true; in amdgpu_pm_sysfs_init()
4757 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); in amdgpu_pm_sysfs_init()
4759 if (adev->pm.int_hwmon_dev) in amdgpu_pm_sysfs_init()
4760 hwmon_device_unregister(adev->pm.int_hwmon_dev); in amdgpu_pm_sysfs_init()
4769 if (adev->pm.int_hwmon_dev) in amdgpu_pm_sysfs_fini()
4770 hwmon_device_unregister(adev->pm.int_hwmon_dev); in amdgpu_pm_sysfs_fini()
4772 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); in amdgpu_pm_sysfs_fini()
4832 if (adev->flags & AMD_IS_APU) in amdgpu_debugfs_pm_info_pp()
4839 if (adev->flags & AMD_IS_APU) in amdgpu_debugfs_pm_info_pp()
4961 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; in amdgpu_debugfs_pm_info_show()
4990 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
4997 struct amdgpu_device *adev = file_inode(f)->i_private; in amdgpu_pm_prv_buffer_read()
5011 return -EINVAL; in amdgpu_pm_prv_buffer_read()
5029 struct drm_minor *minor = adev_to_drm(adev)->primary; in amdgpu_debugfs_pm_init()
5030 struct dentry *root = minor->debugfs_root; in amdgpu_debugfs_pm_init()
5032 if (!adev->pm.dpm_enabled) in amdgpu_debugfs_pm_init()
5038 if (adev->pm.smu_prv_buffer_size > 0) in amdgpu_debugfs_pm_init()
5042 adev->pm.smu_prv_buffer_size); in amdgpu_debugfs_pm_init()