Lines Matching full:enum

48  * CP_PERFMON_ENABLE_MODE enum
51 typedef enum CP_PERFMON_ENABLE_MODE {
59  * CP_PERFMON_STATE enum
62 typedef enum CP_PERFMON_STATE {
72  * ENUM_NUM_SIMD_PER_CU enum
75 typedef enum ENUM_NUM_SIMD_PER_CU {
80  * GATCL1RequestType enum
83 typedef enum GATCL1RequestType {
90  * GL0V_CACHE_POLICIES enum
93 typedef enum GL0V_CACHE_POLICIES {
102  * GL1_CACHE_POLICIES enum
105 typedef enum GL1_CACHE_POLICIES {
113  * GL1_CACHE_STORE_POLICIES enum
116 typedef enum GL1_CACHE_STORE_POLICIES {
121  * GL2_CACHE_POLICIES enum
124 typedef enum GL2_CACHE_POLICIES {
132  * GL2_NACKS enum
135 typedef enum GL2_NACKS {
143  * GL2_OP enum
146 typedef enum GL2_OP {
254  * GL2_OP_MASKS enum
257 typedef enum GL2_OP_MASKS {
264  * Hdp_SurfaceEndian enum
267 typedef enum Hdp_SurfaceEndian {
275  * MTYPE enum
278 typedef enum MTYPE {
290  * PERFMON_COUNTER_MODE enum
293 typedef enum PERFMON_COUNTER_MODE {
308  * PERFMON_SPM_MODE enum
311 typedef enum PERFMON_SPM_MODE {
326  * READ_COMPRESSION_MODE enum
329 typedef enum READ_COMPRESSION_MODE {
336  * ReadPolicy enum
339 typedef enum ReadPolicy {
347  * SCOPE enum
350 typedef enum SCOPE {
358  * SDMA_PERFMON_SEL enum
361 typedef enum SDMA_PERFMON_SEL {
461  * SDMA_PERF_SEL enum
464 typedef enum SDMA_PERF_SEL {
594  * SPM_PERFMON_STATE enum
597 typedef enum SPM_PERFMON_STATE {
607  * TCC_MTYPE enum
610 typedef enum TCC_MTYPE {
617  * UTCL0FaultType enum
620 typedef enum UTCL0FaultType {
628  * UTCL0RequestType enum
631 typedef enum UTCL0RequestType {
638  * UTCL1FaultType enum
641 typedef enum UTCL1FaultType {
649  * UTCL1RequestType enum
652 typedef enum UTCL1RequestType {
659  * WRITE_COMPRESSION_MODE enum
662 typedef enum WRITE_COMPRESSION_MODE {
669  * WritePolicy enum
672 typedef enum WritePolicy {
680  * COLOR_KEYER_ENABLE enum
683 typedef enum COLOR_KEYER_ENABLE {
689  * COLOR_KEYER_MODE enum
692 typedef enum COLOR_KEYER_MODE {
700  * DENORM_TRUNCATE enum
703 typedef enum DENORM_TRUNCATE {
709  * FORMAT_CROSSBAR enum
712 typedef enum FORMAT_CROSSBAR {
719  * LUMA_KEYER_ENABLE enum
722 typedef enum LUMA_KEYER_ENABLE {
728  * PIX_EXPAND_MODE enum
731 typedef enum PIX_EXPAND_MODE {
737  * PRE_CSC_MODE_ENUM enum
740 typedef enum PRE_CSC_MODE_ENUM {
747  * PRE_DEGAM_MODE enum
750 typedef enum PRE_DEGAM_MODE {
756  * PRE_DEGAM_SELECT enum
759 typedef enum PRE_DEGAM_SELECT {
770  * SURFACE_PIXEL_FORMAT enum
773 typedef enum SURFACE_PIXEL_FORMAT {
852  * XNORM enum
855 typedef enum XNORM {
861  * CUR_ENABLE enum
864 typedef enum CUR_ENABLE {
870  * CUR_EXPAND_MODE enum
873 typedef enum CUR_EXPAND_MODE {
879  * CUR_INV_CLAMP enum
882 typedef enum CUR_INV_CLAMP {
888  * CUR_MATRIX_COEF_FORMAT_ENUM enum
891 typedef enum CUR_MATRIX_COEF_FORMAT_ENUM {
897  * CUR_MODE enum
900 typedef enum CUR_MODE {
910  * CUR_PENDING enum
913 typedef enum CUR_PENDING {
919  * CUR_ROM_EN enum
922 typedef enum CUR_ROM_EN {
928  * COEF_RAM_SELECT_RD enum
931 typedef enum COEF_RAM_SELECT_RD {
937  * DSCL_MODE_SEL enum
940 typedef enum DSCL_MODE_SEL {
951  * ISHARP_FMT_MODE_ENUM enum
954 typedef enum ISHARP_FMT_MODE_ENUM {
960  * ISHARP_LBA_MODE_ENUM enum
963 typedef enum ISHARP_LBA_MODE_ENUM {
969  * ISHARP_NOISEDET_MODE_ENUM enum
972 typedef enum ISHARP_NOISEDET_MODE_ENUM {
980  * LB_ALPHA_EN enum
983 typedef enum LB_ALPHA_EN {
989  * LB_INTERLEAVE_EN enum
992 typedef enum LB_INTERLEAVE_EN {
998  * LB_MEMORY_CONFIG enum
1001 typedef enum LB_MEMORY_CONFIG {
1009  * MATRIX_MODE_ENUM enum
1012 typedef enum MATRIX_MODE_ENUM {
1018  * OBUF_BYPASS_SEL enum
1021 typedef enum OBUF_BYPASS_SEL {
1027  * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
1030 typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
1036  * OBUF_USE_FULL_BUFFER_SEL enum
1039 typedef enum OBUF_USE_FULL_BUFFER_SEL {
1045  * SCL_2TAP_HARDCODE enum
1048 typedef enum SCL_2TAP_HARDCODE {
1054  * SCL_ALPHA_COEF enum
1057 typedef enum SCL_ALPHA_COEF {
1063  * SCL_AUTOCAL_MODE enum
1066 typedef enum SCL_AUTOCAL_MODE {
1074  * SCL_BOUNDARY enum
1077 typedef enum SCL_BOUNDARY {
1083  * SCL_CHROMA_COEF enum
1086 typedef enum SCL_CHROMA_COEF {
1092  * SCL_COEF_FILTER_TYPE_SEL enum
1095 typedef enum SCL_COEF_FILTER_TYPE_SEL {
1105  * SCL_COEF_RAM_SEL enum
1108 typedef enum SCL_COEF_RAM_SEL {
1114  * SCL_SHARP_EN enum
1117 typedef enum SCL_SHARP_EN {
1127  * CMC_3DLUT_30BIT_ENUM enum
1130 typedef enum CMC_3DLUT_30BIT_ENUM {
1136  * CMC_3DLUT_RAM_SEL enum
1139 typedef enum CMC_3DLUT_RAM_SEL {
1147  * CMC_3DLUT_SIZE_ENUM enum
1150 typedef enum CMC_3DLUT_SIZE_ENUM {
1156  * CMC_LUT_2_CONFIG_ENUM enum
1159 typedef enum CMC_LUT_2_CONFIG_ENUM {
1166  * CMC_LUT_2_MODE_ENUM enum
1169 typedef enum CMC_LUT_2_MODE_ENUM {
1176  * CMC_LUT_NUM_SEG enum
1179 typedef enum CMC_LUT_NUM_SEG {
1191  * CMC_LUT_RAM_SEL enum
1194 typedef enum CMC_LUT_RAM_SEL {
1200  * CM_BYPASS enum
1203 typedef enum CM_BYPASS {
1209  * CM_COEF_FORMAT_ENUM enum
1212 typedef enum CM_COEF_FORMAT_ENUM {
1218  * CM_DATA_SIGNED enum
1221 typedef enum CM_DATA_SIGNED {
1227  * CM_EN enum
1230 typedef enum CM_EN {
1236  * CM_GAMMA_LUT_MODE_ENUM enum
1239 typedef enum CM_GAMMA_LUT_MODE_ENUM {
1247  * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum
1250 typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM {
1256  * CM_GAMMA_LUT_SEL_ENUM enum
1259 typedef enum CM_GAMMA_LUT_SEL_ENUM {
1265  * CM_LUT_2_CONFIG_ENUM enum
1268 typedef enum CM_LUT_2_CONFIG_ENUM {
1275  * CM_LUT_2_MODE_ENUM enum
1278 typedef enum CM_LUT_2_MODE_ENUM {
1285  * CM_LUT_4_CONFIG_ENUM enum
1288 typedef enum CM_LUT_4_CONFIG_ENUM {
1297  * CM_LUT_4_MODE_ENUM enum
1300 typedef enum CM_LUT_4_MODE_ENUM {
1309  * CM_LUT_CONFIG_MODE enum
1312 typedef enum CM_LUT_CONFIG_MODE {
1318  * CM_LUT_NUM_SEG enum
1321 typedef enum CM_LUT_NUM_SEG {
1333  * CM_LUT_RAM_SEL enum
1336 typedef enum CM_LUT_RAM_SEL {
1342  * CM_LUT_READ_COLOR_SEL enum
1345 typedef enum CM_LUT_READ_COLOR_SEL {
1352  * CM_LUT_READ_DBG enum
1355 typedef enum CM_LUT_READ_DBG {
1361  * CM_PENDING enum
1364 typedef enum CM_PENDING {
1370  * CM_POST_CSC_MODE_ENUM enum
1373 typedef enum CM_POST_CSC_MODE_ENUM {
1380  * CM_WRITE_BASE_ONLY enum
1383 typedef enum CM_WRITE_BASE_ONLY {
1393  * CRC_CUR_SEL enum
1396 typedef enum CRC_CUR_SEL {
1402  * CRC_INTERLACE_SEL enum
1405 typedef enum CRC_INTERLACE_SEL {
1413  * CRC_IN_PIX_SEL enum
1416 typedef enum CRC_IN_PIX_SEL {
1428  * CRC_SRC_SEL enum
1431 typedef enum CRC_SRC_SEL {
1439  * CRC_STEREO_SEL enum
1442 typedef enum CRC_STEREO_SEL {
1450  * TEST_CLK_SEL enum
1453 typedef enum TEST_CLK_SEL {
1469  * PERFCOUNTER_ACTIVE enum
1472 typedef enum PERFCOUNTER_ACTIVE {
1478  * PERFCOUNTER_CNT0_STATE enum
1481 typedef enum PERFCOUNTER_CNT0_STATE {
1489  * PERFCOUNTER_CNT1_STATE enum
1492 typedef enum PERFCOUNTER_CNT1_STATE {
1500  * PERFCOUNTER_CNT2_STATE enum
1503 typedef enum PERFCOUNTER_CNT2_STATE {
1511  * PERFCOUNTER_CNT3_STATE enum
1514 typedef enum PERFCOUNTER_CNT3_STATE {
1522  * PERFCOUNTER_CNT4_STATE enum
1525 typedef enum PERFCOUNTER_CNT4_STATE {
1533  * PERFCOUNTER_CNT5_STATE enum
1536 typedef enum PERFCOUNTER_CNT5_STATE {
1544  * PERFCOUNTER_CNT6_STATE enum
1547 typedef enum PERFCOUNTER_CNT6_STATE {
1555  * PERFCOUNTER_CNT7_STATE enum
1558 typedef enum PERFCOUNTER_CNT7_STATE {
1566  * PERFCOUNTER_CNTL_SEL enum
1569 typedef enum PERFCOUNTER_CNTL_SEL {
1581  * PERFCOUNTER_CNTOFF_START_DIS enum
1584 typedef enum PERFCOUNTER_CNTOFF_START_DIS {
1590  * PERFCOUNTER_COUNTED_VALUE_TYPE enum
1593 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
1600  * PERFCOUNTER_CVALUE_SEL enum
1603 typedef enum PERFCOUNTER_CVALUE_SEL {
1615  * PERFCOUNTER_HW_CNTL_SEL enum
1618 typedef enum PERFCOUNTER_HW_CNTL_SEL {
1624  * PERFCOUNTER_HW_STOP1_SEL enum
1627 typedef enum PERFCOUNTER_HW_STOP1_SEL {
1633  * PERFCOUNTER_HW_STOP2_SEL enum
1636 typedef enum PERFCOUNTER_HW_STOP2_SEL {
1642  * PERFCOUNTER_INC_MODE enum
1645 typedef enum PERFCOUNTER_INC_MODE {
1654  * PERFCOUNTER_INT_EN enum
1657 typedef enum PERFCOUNTER_INT_EN {
1663  * PERFCOUNTER_INT_TYPE enum
1666 typedef enum PERFCOUNTER_INT_TYPE {
1672  * PERFCOUNTER_OFF_MASK enum
1675 typedef enum PERFCOUNTER_OFF_MASK {
1681  * PERFCOUNTER_RESTART_EN enum
1684 typedef enum PERFCOUNTER_RESTART_EN {
1690  * PERFCOUNTER_RUNEN_MODE enum
1693 typedef enum PERFCOUNTER_RUNEN_MODE {
1699  * PERFCOUNTER_STATE_SEL0 enum
1702 typedef enum PERFCOUNTER_STATE_SEL0 {
1708  * PERFCOUNTER_STATE_SEL1 enum
1711 typedef enum PERFCOUNTER_STATE_SEL1 {
1717  * PERFCOUNTER_STATE_SEL2 enum
1720 typedef enum PERFCOUNTER_STATE_SEL2 {
1726  * PERFCOUNTER_STATE_SEL3 enum
1729 typedef enum PERFCOUNTER_STATE_SEL3 {
1735  * PERFCOUNTER_STATE_SEL4 enum
1738 typedef enum PERFCOUNTER_STATE_SEL4 {
1744  * PERFCOUNTER_STATE_SEL5 enum
1747 typedef enum PERFCOUNTER_STATE_SEL5 {
1753  * PERFCOUNTER_STATE_SEL6 enum
1756 typedef enum PERFCOUNTER_STATE_SEL6 {
1762  * PERFCOUNTER_STATE_SEL7 enum
1765 typedef enum PERFCOUNTER_STATE_SEL7 {
1771  * PERFMON_CNTOFF_AND_OR enum
1774 typedef enum PERFMON_CNTOFF_AND_OR {
1780  * PERFMON_CNTOFF_INT_EN enum
1783 typedef enum PERFMON_CNTOFF_INT_EN {
1789  * PERFMON_CNTOFF_INT_TYPE enum
1792 typedef enum PERFMON_CNTOFF_INT_TYPE {
1798  * PERFMON_STATE enum
1801 typedef enum PERFMON_STATE {
1813  * BIGK_FRAGMENT_SIZE enum
1816 typedef enum BIGK_FRAGMENT_SIZE {
1836  * CHUNK_SIZE enum
1839 typedef enum CHUNK_SIZE {
1850  * DPTE_GROUP_SIZE enum
1853 typedef enum DPTE_GROUP_SIZE {
1863  * FORCE_ONE_ROW_FOR_FRAME enum
1866 typedef enum FORCE_ONE_ROW_FOR_FRAME {
1872  * HUBP_BLANK_EN enum
1875 typedef enum HUBP_BLANK_EN {
1881  * HUBP_IN_BLANK enum
1884 typedef enum HUBP_IN_BLANK {
1890  * HUBP_MEASURE_WIN_MODE_DCFCLK enum
1893 typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
1901  * HUBP_NO_OUTSTANDING_REQ enum
1904 typedef enum HUBP_NO_OUTSTANDING_REQ {
1910  * HUBP_SOFT_RESET enum
1913 typedef enum HUBP_SOFT_RESET {
1919  * HUBP_TTU_DISABLE enum
1922 typedef enum HUBP_TTU_DISABLE {
1928  * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
1931 typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
1937  * HUBP_VTG_SEL enum
1940 typedef enum HUBP_VTG_SEL {
1950  * H_MIRROR_EN enum
1953 typedef enum H_MIRROR_EN {
1959  * LEGACY_PIPE_INTERLEAVE enum
1962 typedef enum LEGACY_PIPE_INTERLEAVE {
1968  * META_CHUNK_SIZE enum
1971 typedef enum META_CHUNK_SIZE {
1979  * META_LINEAR enum
1982 typedef enum META_LINEAR {
1988  * MIN_CHUNK_SIZE enum
1991 typedef enum MIN_CHUNK_SIZE {
1999  * MIN_META_CHUNK_SIZE enum
2002 typedef enum MIN_META_CHUNK_SIZE {
2010  * PIPE_ALIGNED enum
2013 typedef enum PIPE_ALIGNED {
2019  * PTE_BUFFER_MODE enum
2022 typedef enum PTE_BUFFER_MODE {
2028  * PTE_ROW_HEIGHT_LINEAR enum
2031 typedef enum PTE_ROW_HEIGHT_LINEAR {
2043  * ROTATION_ANGLE enum
2046 typedef enum ROTATION_ANGLE {
2054  * SWATH_HEIGHT enum
2057 typedef enum SWATH_HEIGHT {
2066  * VMPG_SIZE enum
2069 typedef enum VMPG_SIZE {
2075  * VM_GROUP_SIZE enum
2078 typedef enum VM_GROUP_SIZE {
2092  * DFQ_MIN_FREE_ENTRIES enum
2095 typedef enum DFQ_MIN_FREE_ENTRIES {
2107  * DFQ_NUM_ENTRIES enum
2110 typedef enum DFQ_NUM_ENTRIES {
2123  * DFQ_SIZE enum
2126 typedef enum DFQ_SIZE {
2138  * DMDATA_VM_DONE enum
2141 typedef enum DMDATA_VM_DONE {
2147  * EXPANSION_MODE enum
2150 typedef enum EXPANSION_MODE {
2157  * FLIP_RATE enum
2160 typedef enum FLIP_RATE {
2172  * INT_MASK enum
2175 typedef enum INT_MASK {
2181  * PIPE_IN_FLUSH_URGENT enum
2184 typedef enum PIPE_IN_FLUSH_URGENT {
2190  * PRQ_MRQ_FLUSH_URGENT enum
2193 typedef enum PRQ_MRQ_FLUSH_URGENT {
2199  * ROW_TTU_MODE enum
2202 typedef enum ROW_TTU_MODE {
2208  * SURFACE_DCC enum
2211 typedef enum SURFACE_DCC {
2217  * SURFACE_DCC_IND_128B enum
2220 typedef enum SURFACE_DCC_IND_128B {
2226  * SURFACE_DCC_IND_64B enum
2229 typedef enum SURFACE_DCC_IND_64B {
2235  * SURFACE_DCC_IND_BLK enum
2238 typedef enum SURFACE_DCC_IND_BLK {
2246  * SURFACE_FLIP_AWAY_INT_TYPE enum
2249 typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
2255  * SURFACE_FLIP_EXEC_DEBUG_MODE enum
2258 typedef enum SURFACE_FLIP_EXEC_DEBUG_MODE {
2264  * SURFACE_FLIP_INT_TYPE enum
2267 typedef enum SURFACE_FLIP_INT_TYPE {
2273  * SURFACE_FLIP_IN_STEREOSYNC enum
2276 typedef enum SURFACE_FLIP_IN_STEREOSYNC {
2282  * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
2285 typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
2293  * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
2296 typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
2302  * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
2305 typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
2311  * SURFACE_FLIP_TYPE enum
2314 typedef enum SURFACE_FLIP_TYPE {
2320  * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
2323 typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
2343  * SURFACE_INUSE_RAED_NO_LATCH enum
2346 typedef enum SURFACE_INUSE_RAED_NO_LATCH {
2352  * SURFACE_TMZ enum
2355 typedef enum SURFACE_TMZ {
2361  * SURFACE_UPDATE_LOCK enum
2364 typedef enum SURFACE_UPDATE_LOCK {
2374  * CROSSBAR_FOR_ALPHA enum
2377 typedef enum CROSSBAR_FOR_ALPHA {
2385  * CROSSBAR_FOR_CB_B enum
2388 typedef enum CROSSBAR_FOR_CB_B {
2396  * CROSSBAR_FOR_CR_R enum
2399 typedef enum CROSSBAR_FOR_CR_R {
2407  * CROSSBAR_FOR_Y_G enum
2410 typedef enum CROSSBAR_FOR_Y_G {
2418  * DETILE_BUFFER_PACKER_ENABLE enum
2421 typedef enum DETILE_BUFFER_PACKER_ENABLE {
2427  * MEM_PWR_DIS_MODE enum
2430 typedef enum MEM_PWR_DIS_MODE {
2436  * MEM_PWR_FORCE_MODE enum
2439 typedef enum MEM_PWR_FORCE_MODE {
2447  * MEM_PWR_STATUS enum
2450 typedef enum MEM_PWR_STATUS {
2458  * PIPE_INT_MASK_MODE enum
2461 typedef enum PIPE_INT_MASK_MODE {
2467  * PIPE_INT_TYPE_MODE enum
2470 typedef enum PIPE_INT_TYPE_MODE {
2476  * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
2479 typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
2489  * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
2492 typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
2499  * CURSOR_2X_MAGNIFY enum
2502 typedef enum CURSOR_2X_MAGNIFY {
2508  * CURSOR_ENABLE enum
2511 typedef enum CURSOR_ENABLE {
2517  * CURSOR_LINES_PER_CHUNK enum
2520 typedef enum CURSOR_LINES_PER_CHUNK {
2529  * CURSOR_MODE enum
2532 typedef enum CURSOR_MODE {
2542  * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
2545 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
2551  * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
2554 typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
2560  * CURSOR_PITCH enum
2563 typedef enum CURSOR_PITCH {
2570  * CURSOR_REQ_MODE enum
2573 typedef enum CURSOR_REQ_MODE {
2579  * CURSOR_SNOOP enum
2582 typedef enum CURSOR_SNOOP {
2588  * CURSOR_STEREO_EN enum
2591 typedef enum CURSOR_STEREO_EN {
2597  * CURSOR_SURFACE_TMZ enum
2600 typedef enum CURSOR_SURFACE_TMZ {
2606  * CURSOR_SYSTEM enum
2609 typedef enum CURSOR_SYSTEM {
2615  * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
2618 typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
2624  * DMDATA_DONE enum
2627 typedef enum DMDATA_DONE {
2633  * DMDATA_MODE enum
2636 typedef enum DMDATA_MODE {
2642  * DMDATA_QOS_MODE enum
2645 typedef enum DMDATA_QOS_MODE {
2651  * DMDATA_REPEAT enum
2654 typedef enum DMDATA_REPEAT {
2660  * DMDATA_UNDERFLOW enum
2663 typedef enum DMDATA_UNDERFLOW {
2669  * DMDATA_UNDERFLOW_CLEAR enum
2672 typedef enum DMDATA_UNDERFLOW_CLEAR {
2678  * DMDATA_UPDATED enum
2681 typedef enum DMDATA_UPDATED {
2687  * HUBP_3DLUT_ADDRESSING_MODE enum
2690 typedef enum HUBP_3DLUT_ADDRESSING_MODE {
2700  * RESPONSE_STATUS enum
2703 typedef enum RESPONSE_STATUS {
2721  * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum
2724 typedef enum DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE {
2731  * DCHUBBUB_MEM_PWR_DIS_MODE enum
2734 typedef enum DCHUBBUB_MEM_PWR_DIS_MODE {
2740  * DCHUBBUB_MEM_PWR_MODE enum
2743 typedef enum DCHUBBUB_MEM_PWR_MODE {
2755  * MPC_CFG_3DLUT_FL_FORMAT enum
2758 typedef enum MPC_CFG_3DLUT_FL_FORMAT {
2765  * MPC_CFG_3DLUT_FL_MODE enum
2768 typedef enum MPC_CFG_3DLUT_FL_MODE {
2776  * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
2779 typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
2785  * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
2788 typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
2794  * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
2797 typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
2803  * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
2806 typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
2812  * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
2815 typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
2821  * MPC_CFG_MPC_TEST_CLK_SEL enum
2824 typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
2832  * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum
2835 typedef enum MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN {
2841  * MPC_CRC_CALC_INTERLACE_MODE enum
2844 typedef enum MPC_CRC_CALC_INTERLACE_MODE {
2852  * MPC_CRC_CALC_MODE enum
2855 typedef enum MPC_CRC_CALC_MODE {
2861  * MPC_CRC_CALC_STEREO_MODE enum
2864 typedef enum MPC_CRC_CALC_STEREO_MODE {
2872  * MPC_CRC_SOURCE_SELECT enum
2875 typedef enum MPC_CRC_SOURCE_SELECT {
2887  * MPC_OCSC_COEF_FORMAT enum
2890 typedef enum MPC_OCSC_COEF_FORMAT {
2896  * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum
2899 typedef enum MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN {
2905  * MPC_OUT_CSC_MODE enum
2908 typedef enum MPC_OUT_CSC_MODE {
2916  * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
2919 typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
2931  * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
2934 typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
2944  * MPCC_BG_COLOR_BPC enum
2947 typedef enum MPCC_BG_COLOR_BPC {
2956  * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
2959 typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
2965  * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
2968 typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
2976  * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
2979 typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
2985  * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
2988 typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
2994  * MPCC_CONTROL_MPCC_MODE enum
2997 typedef enum MPCC_CONTROL_MPCC_MODE {
3005  * MPCC_SM_CONTROL_MPCC_SM_EN enum
3008 typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
3014  * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
3017 typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
3023  * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
3026 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
3034  * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
3037 typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
3045  * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
3048 typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
3054  * MPCC_SM_CONTROL_MPCC_SM_MODE enum
3057 typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
3069  * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum
3072 typedef enum MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM {
3078  * MPCC_GAMUT_REMAP_MODE_ENUM enum
3081 typedef enum MPCC_GAMUT_REMAP_MODE_ENUM {
3089  * MPCC_OGAM_LUT_2_CONFIG_ENUM enum
3092 typedef enum MPCC_OGAM_LUT_2_CONFIG_ENUM {
3099  * MPCC_OGAM_LUT_CONFIG_MODE enum
3102 typedef enum MPCC_OGAM_LUT_CONFIG_MODE {
3108  * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum
3111 typedef enum MPCC_OGAM_LUT_PWL_DISABLE_ENUM {
3117  * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
3120 typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
3126  * MPCC_OGAM_LUT_RAM_SEL enum
3129 typedef enum MPCC_OGAM_LUT_RAM_SEL {
3135  * MPCC_OGAM_LUT_READ_COLOR_SEL enum
3138 typedef enum MPCC_OGAM_LUT_READ_COLOR_SEL {
3145  * MPCC_OGAM_LUT_READ_DBG enum
3148 typedef enum MPCC_OGAM_LUT_READ_DBG {
3154  * MPCC_OGAM_LUT_SEL_ENUM enum
3157 typedef enum MPCC_OGAM_LUT_SEL_ENUM {
3163  * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum
3166 typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM {
3174  * MPCC_OGAM_NUM_SEG enum
3177 typedef enum MPCC_OGAM_NUM_SEG {
3189  * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum
3192 typedef enum MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN {
3202  * MPCC_MCM_3DLUT_30BIT_ENUM enum
3205 typedef enum MPCC_MCM_3DLUT_30BIT_ENUM {
3211  * MPCC_MCM_3DLUT_RAM_SEL enum
3214 typedef enum MPCC_MCM_3DLUT_RAM_SEL {
3222  * MPCC_MCM_3DLUT_SIZE_ENUM enum
3225 typedef enum MPCC_MCM_3DLUT_SIZE_ENUM {
3231  * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum
3234 typedef enum MPCC_MCM_GAMMA_LUT_MODE_ENUM {
3242  * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum
3245 typedef enum MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM {
3251  * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum
3254 typedef enum MPCC_MCM_GAMMA_LUT_SEL_ENUM {
3260  * MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM enum
3263 typedef enum MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM {
3269  * MPCC_MCM_GAMUT_REMAP_MODE_ENUM enum
3272 typedef enum MPCC_MCM_GAMUT_REMAP_MODE_ENUM {
3280  * MPCC_MCM_LUT_2_MODE_ENUM enum
3283 typedef enum MPCC_MCM_LUT_2_MODE_ENUM {
3290  * MPCC_MCM_LUT_CONFIG_MODE enum
3293 typedef enum MPCC_MCM_LUT_CONFIG_MODE {
3299  * MPCC_MCM_LUT_NUM_SEG enum
3302 typedef enum MPCC_MCM_LUT_NUM_SEG {
3314  * MPCC_MCM_LUT_RAM_SEL enum
3317 typedef enum MPCC_MCM_LUT_RAM_SEL {
3323  * MPCC_MCM_LUT_READ_COLOR_SEL enum
3326 typedef enum MPCC_MCM_LUT_READ_COLOR_SEL {
3333  * MPCC_MCM_LUT_READ_DBG enum
3336 typedef enum MPCC_MCM_LUT_READ_DBG {
3342  * MPCC_MCM_MEM_PWR_FORCE_ENUM enum
3345 typedef enum MPCC_MCM_MEM_PWR_FORCE_ENUM {
3353  * MPCC_MCM_MEM_PWR_STATE_ENUM enum
3356 typedef enum MPCC_MCM_MEM_PWR_STATE_ENUM {
3368  * ENUM_DPG_BIT_DEPTH enum
3371 typedef enum ENUM_DPG_BIT_DEPTH {
3379  * ENUM_DPG_DYNAMIC_RANGE enum
3382 typedef enum ENUM_DPG_DYNAMIC_RANGE {
3388  * ENUM_DPG_EN enum
3391 typedef enum ENUM_DPG_EN {
3397  * ENUM_DPG_FIELD_POLARITY enum
3400 typedef enum ENUM_DPG_FIELD_POLARITY {
3406  * ENUM_DPG_MODE enum
3409 typedef enum ENUM_DPG_MODE {
3425  * FMTMEM_PWR_DIS_CTRL enum
3428 typedef enum FMTMEM_PWR_DIS_CTRL {
3434  * FMTMEM_PWR_FORCE_CTRL enum
3437 typedef enum FMTMEM_PWR_FORCE_CTRL {
3445  * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3448 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3456  * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3459 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3467  * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3470 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3478  * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3481 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3488  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3491 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3498  * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3501 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3507  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3510 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3517  * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3520 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3526  * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3529 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3541  * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3544 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3550  * FMT_CONTROL_PIXEL_ENCODING enum
3553 typedef enum FMT_CONTROL_PIXEL_ENCODING {
3561  * FMT_CONTROL_SUBSAMPLING_MODE enum
3564 typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3572  * FMT_CONTROL_SUBSAMPLING_ORDER enum
3575 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3581  * FMT_DEBUG_CNTL_COLOR_SELECT enum
3584 typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3592  * FMT_DYNAMIC_EXP_MODE enum
3595 typedef enum FMT_DYNAMIC_EXP_MODE {
3601  * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
3604 typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
3610  * FMT_POWER_STATE_ENUM enum
3613 typedef enum FMT_POWER_STATE_ENUM {
3621  * FMT_RGB_RANDOM_ENABLE_CONTROL enum
3624 typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
3630  * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
3633 typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
3641  * FMT_SPATIAL_DITHER_MODE enum
3644 typedef enum FMT_SPATIAL_DITHER_MODE {
3652  * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
3655 typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
3661  * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3664 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3674  * OPPBUF_DISPLAY_SEGMENTATION enum
3677 typedef enum OPPBUF_DISPLAY_SEGMENTATION {
3690  * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
3693 typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
3699  * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
3702 typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
3712  * OPP_PIPE_CRC_CONT_EN enum
3715 typedef enum OPP_PIPE_CRC_CONT_EN {
3721  * OPP_PIPE_CRC_EN enum
3724 typedef enum OPP_PIPE_CRC_EN {
3730  * OPP_PIPE_CRC_INTERLACE_EN enum
3733 typedef enum OPP_PIPE_CRC_INTERLACE_EN {
3739  * OPP_PIPE_CRC_INTERLACE_MODE enum
3742 typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
3750  * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
3753 typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
3759  * OPP_PIPE_CRC_PIXEL_SELECT enum
3762 typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
3770  * OPP_PIPE_CRC_SOURCE_SELECT enum
3773 typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
3779  * OPP_PIPE_CRC_STEREO_EN enum
3782 typedef enum OPP_PIPE_CRC_STEREO_EN {
3788  * OPP_PIPE_CRC_STEREO_MODE enum
3791 typedef enum OPP_PIPE_CRC_STEREO_MODE {
3803  * OPP_TEST_CLK_SEL_CONTROL enum
3806 typedef enum OPP_TEST_CLK_SEL_CONTROL {
3824  * OPP_TOP_CLOCK_ENABLE_STATUS enum
3827 typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
3833  * OPP_TOP_CLOCK_GATING_CONTROL enum
3836 typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
3846  * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
3849 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
3855  * MASTER_UPDATE_LOCK_SEL enum
3858 typedef enum MASTER_UPDATE_LOCK_SEL {
3868  * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
3871 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
3879  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
3882 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
3888  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
3891 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
3897  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
3900 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
3906  * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
3909 typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
3917  * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
3920 typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
3928  * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
3931 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
3937  * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
3940 typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
3946  * OTG_CONTROL_OTG_MASTER_EN enum
3949 typedef enum OTG_CONTROL_OTG_MASTER_EN {
3955  * OTG_CONTROL_OTG_OUT_MUX enum
3958 typedef enum OTG_CONTROL_OTG_OUT_MUX {
3965  * OTG_CONTROL_OTG_START_POINT_CNTL enum
3968 typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
3974  * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
3977 typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
3983  * OTG_CRC_CNTL_OTG_CRC1_EN enum
3986 typedef enum OTG_CRC_CNTL_OTG_CRC1_EN {
3992  * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
3995 typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
4001  * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum
4004 typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_MODE {
4010  * OTG_CRC_CNTL_OTG_CRC_EN enum
4013 typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
4019  * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
4022 typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
4030  * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
4033 typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
4041  * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
4044 typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
4050  * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
4053 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
4065  * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
4068 typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
4080  * OTG_DIG_UPDATE_VCOUNT_MODE enum
4083 typedef enum OTG_DIG_UPDATE_VCOUNT_MODE {
4089  * OTG_DLPC_CONTROL_OTG_RESYNC_MODE enum
4092 typedef enum OTG_DLPC_CONTROL_OTG_RESYNC_MODE {
4098  * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum
4101 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE {
4109  * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
4112 typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
4118  * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
4121 typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
4129  * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
4132 typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
4138  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
4141 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
4147  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
4150 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
4156  * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
4159 typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
4183  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
4186 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
4192  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
4195 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
4201  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
4204 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
4212  * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
4215 typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
4221  * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
4224 typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
4234  * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum
4237 typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL {
4244  * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum
4247 typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL {
4255  * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
4258 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
4266  * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
4269 typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
4277  * OTG_GLOBAL_UPDATE_LOCK_EN enum
4280 typedef enum OTG_GLOBAL_UPDATE_LOCK_EN {
4286  * OTG_GSL_MASTER_MODE enum
4289 typedef enum OTG_GSL_MASTER_MODE {
4297  * OTG_HORZ_REPETITION_COUNT enum
4300 typedef enum OTG_HORZ_REPETITION_COUNT {
4320  * OTG_H_SYNC_A_POL enum
4323 typedef enum OTG_H_SYNC_A_POL {
4329  * OTG_H_TIMING_DIV_MODE enum
4332 typedef enum OTG_H_TIMING_DIV_MODE {
4340  * OTG_H_TIMING_DIV_MODE_MANUAL enum
4343 typedef enum OTG_H_TIMING_DIV_MODE_MANUAL {
4349  * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
4352 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
4358  * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
4361 typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
4369  * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
4372 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
4378  * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
4381 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
4387  * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
4390 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
4396  * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
4399 typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
4405  * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
4408 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
4414  * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
4417 typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
4423  * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
4426 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
4432  * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
4435 typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
4441  * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
4444 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
4450  * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
4453 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
4459  * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
4462 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
4468  * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
4471 typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
4477  * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
4480 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
4486  * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
4489 typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
4495  * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
4498 typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
4504  * OTG_MASTER_UPDATE_LOCK_DB_EN enum
4507 typedef enum OTG_MASTER_UPDATE_LOCK_DB_EN {
4513  * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
4516 typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
4522  * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum
4525 typedef enum OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE {
4531  * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
4534 typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
4542  * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
4545 typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
4551  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
4554 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
4560  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
4563 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
4569  * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
4572 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
4578  * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
4581 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
4587  * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
4590 typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
4596  * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum
4599 typedef enum OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL {
4605  * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
4608 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
4614  * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
4617 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
4623  * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
4626 typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
4632  * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
4635 typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
4643  * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
4646 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
4652  * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
4655 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
4667  * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
4670 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
4676  * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
4679 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
4689  * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
4692 typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
4721  * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
4724 typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
4732  * OTG_TRIGA_FREQUENCY_SELECT enum
4735 typedef enum OTG_TRIGA_FREQUENCY_SELECT {
4743  * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
4746 typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
4754  * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
4757 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
4763  * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
4766 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
4778  * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
4781 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
4787  * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
4790 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
4800  * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
4803 typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
4832  * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
4835 typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
4843  * OTG_TRIGB_FREQUENCY_SELECT enum
4846 typedef enum OTG_TRIGB_FREQUENCY_SELECT {
4854  * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
4857 typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
4865  * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
4868 typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
4874  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
4877 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
4883  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
4886 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
4892  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
4895 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
4901  * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
4904 typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
4910  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
4913 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
4919  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
4922 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
4928  * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
4931 typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
4937  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
4940 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
4946  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
4949 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
4955  * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
4958 typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
4964  * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
4967 typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
4975  * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
4978 typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
4984  * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
4987 typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
4993  * OTG_VUPDATE_BLOCK_DISABLE enum
4996 typedef enum OTG_VUPDATE_BLOCK_DISABLE {
5002  * OTG_V_SYNC_A_POL enum
5005 typedef enum OTG_V_SYNC_A_POL {
5011  * OTG_V_SYNC_MODE enum
5014 typedef enum OTG_V_SYNC_MODE {
5020  * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
5023 typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
5029  * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
5032 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
5038  * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
5041 typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
5047  * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
5050 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
5056  * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
5059 typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
5065  * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum
5068 typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK {
5078  * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum
5081 typedef enum OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL {
5095  * DC_DMCUB_INT_TYPE enum
5098 typedef enum DC_DMCUB_INT_TYPE {
5104  * DC_DMCUB_TIMER_WINDOW enum
5107 typedef enum DC_DMCUB_TIMER_WINDOW {
5123  * INVALID_REG_ACCESS_TYPE enum
5126 typedef enum INVALID_REG_ACCESS_TYPE {
5140  * DMU_DC_GPU_TIMER_READ_SELECT enum
5143 typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
5239  * DMU_DC_GPU_TIMER_START_POSITION enum
5242 typedef enum DMU_DC_GPU_TIMER_START_POSITION {
5254  * IHC_INTERRUPT_DEST enum
5257 typedef enum IHC_INTERRUPT_DEST {
5263  * IHC_INTERRUPT_LINE_STATUS enum
5266 typedef enum IHC_INTERRUPT_LINE_STATUS {
5276  * DC_SMU_INTERRUPT_ENABLE enum
5279 typedef enum DC_SMU_INTERRUPT_ENABLE {
5285  * DMU_CLOCK_ON enum
5288 typedef enum DMU_CLOCK_ON {
5294  * SMU_INTR enum
5297 typedef enum SMU_INTR {
5307  * ALLOW_SR_ON_TRANS_REQ enum
5310 typedef enum ALLOW_SR_ON_TRANS_REQ {
5316  * AMCLOCK_ENABLE enum
5319 typedef enum AMCLOCK_ENABLE {
5325  * CLEAR_SMU_INTR enum
5328 typedef enum CLEAR_SMU_INTR {
5334  * CLOCK_BRANCH_SOFT_RESET enum
5337 typedef enum CLOCK_BRANCH_SOFT_RESET {
5343  * DCCG_AUDIO_DTO0_SOURCE_SEL enum
5346 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
5355  * DCCG_AUDIO_DTO2_SOURCE_SEL enum
5358 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
5364  * DCCG_AUDIO_DTO_SEL enum
5367 typedef enum DCCG_AUDIO_DTO_SEL {
5374  * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
5377 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
5383  * DCCG_DBG_BLOCK_SEL enum
5386 typedef enum DCCG_DBG_BLOCK_SEL {
5393  * DCCG_DBG_EN enum
5396 typedef enum DCCG_DBG_EN {
5402  * DCCG_DEEP_COLOR_CNTL enum
5405 typedef enum DCCG_DEEP_COLOR_CNTL {
5413  * DCCG_FIFO_ERRDET_OVR_EN enum
5416 typedef enum DCCG_FIFO_ERRDET_OVR_EN {
5422  * DCCG_FIFO_ERRDET_RESET enum
5425 typedef enum DCCG_FIFO_ERRDET_RESET {
5431  * DCCG_FIFO_ERRDET_STATE enum
5434 typedef enum DCCG_FIFO_ERRDET_STATE {
5440  * DCCG_PERF_MODE_HSYNC enum
5443 typedef enum DCCG_PERF_MODE_HSYNC {
5449  * DCCG_PERF_MODE_VSYNC enum
5452 typedef enum DCCG_PERF_MODE_VSYNC {
5458  * DCCG_PERF_OTG_SELECT enum
5461 typedef enum DCCG_PERF_OTG_SELECT {
5470  * DCCG_PERF_RUN enum
5473 typedef enum DCCG_PERF_RUN {
5479  * DC_MEM_GLOBAL_PWR_REQ_DIS enum
5482 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
5488  * DIO_FIFO_ERROR enum
5491 typedef enum DIO_FIFO_ERROR {
5499  * DISABLE_CLOCK_GATING enum
5502 typedef enum DISABLE_CLOCK_GATING {
5508  * DISABLE_CLOCK_GATING_IN_DCO enum
5511 typedef enum DISABLE_CLOCK_GATING_IN_DCO {
5517  * DISPCLK_CHG_FWD_CORR_DISABLE enum
5520 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
5526  * DISPCLK_FREQ_RAMP_DONE enum
5529 typedef enum DISPCLK_FREQ_RAMP_DONE {
5535  * DPREFCLK_SRC_SEL enum
5538 typedef enum DPREFCLK_SRC_SEL {
5546  * DP_DTO_DS_DISABLE enum
5549 typedef enum DP_DTO_DS_DISABLE {
5555  * DS_HW_CAL_ENABLE enum
5558 typedef enum DS_HW_CAL_ENABLE {
5564  * DS_REF_SRC enum
5567 typedef enum DS_REF_SRC {
5574  * DVO_ENABLE_RST enum
5577 typedef enum DVO_ENABLE_RST {
5583  * ENABLE enum
5586 typedef enum ENABLE {
5592  * ENABLE_CLOCK enum
5595 typedef enum ENABLE_CLOCK {
5601  * FORCE_DISABLE_CLOCK enum
5604 typedef enum FORCE_DISABLE_CLOCK {
5610  * HDMICHARCLK_SRC_SEL enum
5613 typedef enum HDMICHARCLK_SRC_SEL {
5622  * HDMISTREAMCLK_SRC_SEL enum
5625 typedef enum HDMISTREAMCLK_SRC_SEL {
5633  * JITTER_REMOVE_DISABLE enum
5636 typedef enum JITTER_REMOVE_DISABLE {
5642  * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5645 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5651  * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5654 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5660  * OTG_ADD_PIXEL enum
5663 typedef enum OTG_ADD_PIXEL {
5669  * OTG_DROP_PIXEL enum
5672 typedef enum OTG_DROP_PIXEL {
5678  * PHYSYMCLK_FORCE_EN enum
5681 typedef enum PHYSYMCLK_FORCE_EN {
5687  * PHYSYMCLK_FORCE_SRC_SEL enum
5690 typedef enum PHYSYMCLK_FORCE_SRC_SEL {
5697  * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
5700 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
5709  * PIPE_PIXEL_RATE_PLL_SOURCE enum
5712 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
5718  * PIPE_PIXEL_RATE_SOURCE enum
5721 typedef enum PIPE_PIXEL_RATE_SOURCE {
5728  * PLL_CFG_IF_SOFT_RESET enum
5731 typedef enum PLL_CFG_IF_SOFT_RESET {
5737  * SYMCLK_FE_SRC enum
5740 typedef enum SYMCLK_FE_SRC {
5749  * TEST_CLK_DIV_SEL enum
5752 typedef enum TEST_CLK_DIV_SEL {
5760  * VSYNC_CNT_LATCH_MASK enum
5763 typedef enum VSYNC_CNT_LATCH_MASK {
5769  * VSYNC_CNT_RESET_SEL enum
5772 typedef enum VSYNC_CNT_RESET_SEL {
5778  * XTAL_REF_CLOCK_SOURCE_SEL enum
5781 typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
5787  * XTAL_REF_SEL enum
5790 typedef enum XTAL_REF_SEL {
5800  * DPHY_8B10B_CUR_DISP enum
5803 typedef enum DPHY_8B10B_CUR_DISP {
5809  * DPHY_8B10B_RESET enum
5812 typedef enum DPHY_8B10B_RESET {
5818  * DPHY_ATEST_SEL_LANE0 enum
5821 typedef enum DPHY_ATEST_SEL_LANE0 {
5827  * DPHY_ATEST_SEL_LANE1 enum
5830 typedef enum DPHY_ATEST_SEL_LANE1 {
5836  * DPHY_ATEST_SEL_LANE2 enum
5839 typedef enum DPHY_ATEST_SEL_LANE2 {
5845  * DPHY_ATEST_SEL_LANE3 enum
5848 typedef enum DPHY_ATEST_SEL_LANE3 {
5854  * DPHY_BYPASS enum
5857 typedef enum DPHY_BYPASS {
5863  * DPHY_CRC_CONT_EN enum
5866 typedef enum DPHY_CRC_CONT_EN {
5872  * DPHY_CRC_EN enum
5875 typedef enum DPHY_CRC_EN {
5881  * DPHY_CRC_FIELD enum
5884 typedef enum DPHY_CRC_FIELD {
5890  * DPHY_CRC_MST_PHASE_ERROR_ACK enum
5893 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
5899  * DPHY_CRC_SEL enum
5902 typedef enum DPHY_CRC_SEL {
5910  * DPHY_FEC_ENABLE enum
5913 typedef enum DPHY_FEC_ENABLE {
5919  * DPHY_FEC_READY enum
5922 typedef enum DPHY_FEC_READY {
5928  * DPHY_LOAD_BS_COUNT_START enum
5931 typedef enum DPHY_LOAD_BS_COUNT_START {
5937  * DPHY_PRBS_EN enum
5940 typedef enum DPHY_PRBS_EN {
5946  * DPHY_PRBS_SEL enum
5949 typedef enum DPHY_PRBS_SEL {
5956  * DPHY_RX_FAST_TRAINING_CAPABLE enum
5959 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
5965  * DPHY_SKEW_BYPASS enum
5968 typedef enum DPHY_SKEW_BYPASS {
5974  * DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM enum
5977 typedef enum DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM {
5983  * DPHY_SW_FAST_TRAINING_START enum
5986 typedef enum DPHY_SW_FAST_TRAINING_START {
5992  * DPHY_TRAINING_PATTERN_SEL enum
5995 typedef enum DPHY_TRAINING_PATTERN_SEL {
6003  * DP_COMPONENT_DEPTH enum
6006 typedef enum DP_COMPONENT_DEPTH {
6015  * DP_COMPRESSED_PIXEL_FORMAT enum
6018 typedef enum DP_COMPRESSED_PIXEL_FORMAT {
6024  * DP_DPHY_8B10B_EXT_DISP enum
6027 typedef enum DP_DPHY_8B10B_EXT_DISP {
6033  * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
6036 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
6042  * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
6045 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
6051  * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
6054 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
6060  * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
6063 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
6072  * DP_LINK_TRAINING_COMPLETE enum
6075 typedef enum DP_LINK_TRAINING_COMPLETE {
6081  * DP_LINK_TRAINING_SWITCH_MODE enum
6084 typedef enum DP_LINK_TRAINING_SWITCH_MODE {
6090  * DP_ML_PHY_SEQ_MODE enum
6093 typedef enum DP_ML_PHY_SEQ_MODE {
6099  * DP_MSA_V_TIMING_OVERRIDE_EN enum
6102 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
6108  * DP_MSE_BLANK_CODE enum
6111 typedef enum DP_MSE_BLANK_CODE {
6117  * DP_MSE_LINK_LINE enum
6120 typedef enum DP_MSE_LINK_LINE {
6128  * DP_MSE_TIMESTAMP_MODE enum
6131 typedef enum DP_MSE_TIMESTAMP_MODE {
6137  * DP_MSE_ZERO_ENCODER enum
6140 typedef enum DP_MSE_ZERO_ENCODER {
6146  * DP_MSO_NUM_OF_SST_LINKS enum
6149 typedef enum DP_MSO_NUM_OF_SST_LINKS {
6156  * DP_PIXEL_ENCODING enum
6159 typedef enum DP_PIXEL_ENCODING {
6167  * DP_PIXEL_ENCODING_TYPE enum
6170 typedef enum DP_PIXEL_ENCODING_TYPE {
6176  * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
6179 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
6185  * DP_SEC_ASP_PRIORITY enum
6188 typedef enum DP_SEC_ASP_PRIORITY {
6194  * DP_SEC_AUDIO_MUTE enum
6197 typedef enum DP_SEC_AUDIO_MUTE {
6203  * DP_SEC_COLLISION_ACK enum
6206 typedef enum DP_SEC_COLLISION_ACK {
6212  * DP_SEC_GSP0_PRIORITY enum
6215 typedef enum DP_SEC_GSP0_PRIORITY {
6221  * DP_SEC_GSP_SEND enum
6224 typedef enum DP_SEC_GSP_SEND {
6230  * DP_SEC_GSP_SEND_ANY_LINE enum
6233 typedef enum DP_SEC_GSP_SEND_ANY_LINE {
6239  * DP_SEC_GSP_SEND_PPS enum
6242 typedef enum DP_SEC_GSP_SEND_PPS {
6248  * DP_SEC_LINE_REFERENCE enum
6251 typedef enum DP_SEC_LINE_REFERENCE {
6257  * DP_SEC_TIMESTAMP_MODE enum
6260 typedef enum DP_SEC_TIMESTAMP_MODE {
6266  * DP_STEER_OUTPUT_PIXEL_PER_CYCLE enum
6269 typedef enum DP_STEER_OUTPUT_PIXEL_PER_CYCLE {
6277  * DP_STEER_OVERFLOW_ACK enum
6280 typedef enum DP_STEER_OVERFLOW_ACK {
6286  * DP_STEER_OVERFLOW_MASK enum
6289 typedef enum DP_STEER_OVERFLOW_MASK {
6295  * DP_SYNC_POLARITY enum
6298 typedef enum DP_SYNC_POLARITY {
6304  * DP_TU_OVERFLOW_ACK enum
6307 typedef enum DP_TU_OVERFLOW_ACK {
6313  * DP_UDI_LANES enum
6316 typedef enum DP_UDI_LANES {
6324  * DP_VID_ENHANCED_FRAME_MODE enum
6327 typedef enum DP_VID_ENHANCED_FRAME_MODE {
6333  * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
6336 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
6342  * DP_VID_M_N_GEN_EN enum
6345 typedef enum DP_VID_M_N_GEN_EN {
6351  * DP_VID_N_INTERVAL enum
6354 typedef enum DP_VID_N_INTERVAL {
6362  * DP_VID_STREAM_DISABLE_ACK enum
6365 typedef enum DP_VID_STREAM_DISABLE_ACK {
6371  * DP_VID_STREAM_DISABLE_MASK enum
6374 typedef enum DP_VID_STREAM_DISABLE_MASK {
6380  * DP_VID_STREAM_DIS_DEFER enum
6383 typedef enum DP_VID_STREAM_DIS_DEFER {
6390  * DP_VID_VBID_FIELD_POL enum
6393 typedef enum DP_VID_VBID_FIELD_POL {
6399  * FEC_ACTIVE_STATUS enum
6402 typedef enum FEC_ACTIVE_STATUS {
6412  * DIG_BE_CNTL_HPD_SELECT enum
6415 typedef enum DIG_BE_CNTL_HPD_SELECT {
6424  * DIG_BE_CNTL_MODE enum
6427 typedef enum DIG_BE_CNTL_MODE {
6439  * DIG_DIGITAL_BYPASS_ENABLE enum
6442 typedef enum DIG_DIGITAL_BYPASS_ENABLE {
6448  * DIG_DIGITAL_BYPASS_SEL enum
6451 typedef enum DIG_DIGITAL_BYPASS_SEL {
6462  * DIG_FE_CNTL_SOURCE_SELECT enum
6465 typedef enum DIG_FE_CNTL_SOURCE_SELECT {
6474  * DIG_FE_CNTL_STEREOSYNC_SELECT enum
6477 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
6486  * DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX enum
6489 typedef enum DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX {
6495  * DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL enum
6498 typedef enum DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL {
6504  * DIG_FIFO_FORCE_RECAL_AVERAGE enum
6507 typedef enum DIG_FIFO_FORCE_RECAL_AVERAGE {
6513  * DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE enum
6516 typedef enum DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE {
6524  * DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR enum
6527 typedef enum DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR {
6534  * DIG_FIFO_READ_CLOCK_SRC enum
6537 typedef enum DIG_FIFO_READ_CLOCK_SRC {
6543  * DIG_MODE enum
6546 typedef enum DIG_MODE {
6558  * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
6561 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
6567  * DIG_OUTPUT_CRC_DATA_SEL enum
6570 typedef enum DIG_OUTPUT_CRC_DATA_SEL {
6578  * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
6581 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
6587  * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
6590 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
6596  * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
6599 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
6605  * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
6608 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
6614  * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
6617 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
6623  * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
6626 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
6632  * HDMI_ACP_SEND enum
6635 typedef enum HDMI_ACP_SEND {
6641  * HDMI_ACR_AUDIO_PRIORITY enum
6644 typedef enum HDMI_ACR_AUDIO_PRIORITY {
6650  * HDMI_ACR_CONT enum
6653 typedef enum HDMI_ACR_CONT {
6659  * HDMI_ACR_N_MULTIPLE enum
6662 typedef enum HDMI_ACR_N_MULTIPLE {
6674  * HDMI_ACR_SELECT enum
6677 typedef enum HDMI_ACR_SELECT {
6685  * HDMI_ACR_SEND enum
6688 typedef enum HDMI_ACR_SEND {
6694  * HDMI_ACR_SOURCE enum
6697 typedef enum HDMI_ACR_SOURCE {
6703  * HDMI_AUDIO_DELAY_EN enum
6706 typedef enum HDMI_AUDIO_DELAY_EN {
6714  * HDMI_AUDIO_INFO_CONT enum
6717 typedef enum HDMI_AUDIO_INFO_CONT {
6723  * HDMI_AUDIO_INFO_SEND enum
6726 typedef enum HDMI_AUDIO_INFO_SEND {
6732  * HDMI_CLOCK_CHANNEL_RATE enum
6735 typedef enum HDMI_CLOCK_CHANNEL_RATE {
6741  * HDMI_DATA_SCRAMBLE_EN enum
6744 typedef enum HDMI_DATA_SCRAMBLE_EN {
6750  * HDMI_DEEP_COLOR_DEPTH enum
6753 typedef enum HDMI_DEEP_COLOR_DEPTH {
6761  * HDMI_DEFAULT_PAHSE enum
6764 typedef enum HDMI_DEFAULT_PAHSE {
6770  * HDMI_ERROR_ACK enum
6773 typedef enum HDMI_ERROR_ACK {
6779  * HDMI_ERROR_MASK enum
6782 typedef enum HDMI_ERROR_MASK {
6788  * HDMI_GC_AVMUTE enum
6791 typedef enum HDMI_GC_AVMUTE {
6797  * HDMI_GC_AVMUTE_CONT enum
6800 typedef enum HDMI_GC_AVMUTE_CONT {
6806  * HDMI_GC_CONT enum
6809 typedef enum HDMI_GC_CONT {
6815  * HDMI_GC_SEND enum
6818 typedef enum HDMI_GC_SEND {
6824  * HDMI_GENERIC_CONT enum
6827 typedef enum HDMI_GENERIC_CONT {
6833  * HDMI_GENERIC_SEND enum
6836 typedef enum HDMI_GENERIC_SEND {
6842  * HDMI_ISRC_CONT enum
6845 typedef enum HDMI_ISRC_CONT {
6851  * HDMI_ISRC_SEND enum
6854 typedef enum HDMI_ISRC_SEND {
6860  * HDMI_KEEPOUT_MODE enum
6863 typedef enum HDMI_KEEPOUT_MODE {
6869  * HDMI_METADATA_ENABLE enum
6872 typedef enum HDMI_METADATA_ENABLE {
6878  * HDMI_MPEG_INFO_CONT enum
6881 typedef enum HDMI_MPEG_INFO_CONT {
6887  * HDMI_MPEG_INFO_SEND enum
6890 typedef enum HDMI_MPEG_INFO_SEND {
6896  * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
6899 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
6905  * HDMI_NULL_SEND enum
6908 typedef enum HDMI_NULL_SEND {
6914  * HDMI_PACKET_GEN_VERSION enum
6917 typedef enum HDMI_PACKET_GEN_VERSION {
6923  * HDMI_PACKET_LINE_REFERENCE enum
6926 typedef enum HDMI_PACKET_LINE_REFERENCE {
6932  * HDMI_PACKING_PHASE_OVERRIDE enum
6935 typedef enum HDMI_PACKING_PHASE_OVERRIDE {
6941  * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
6944 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
6950  * TMDS_COLOR_FORMAT enum
6953 typedef enum TMDS_COLOR_FORMAT {
6961  * TMDS_CTL0_DATA_INVERT enum
6964 typedef enum TMDS_CTL0_DATA_INVERT {
6970  * TMDS_CTL0_DATA_MODULATION enum
6973 typedef enum TMDS_CTL0_DATA_MODULATION {
6981  * TMDS_CTL0_DATA_SEL enum
6984 typedef enum TMDS_CTL0_DATA_SEL {
6996  * TMDS_CTL0_PATTERN_OUT_EN enum
6999 typedef enum TMDS_CTL0_PATTERN_OUT_EN {
7005  * TMDS_CTL1_DATA_INVERT enum
7008 typedef enum TMDS_CTL1_DATA_INVERT {
7014  * TMDS_CTL1_DATA_MODULATION enum
7017 typedef enum TMDS_CTL1_DATA_MODULATION {
7025  * TMDS_CTL1_DATA_SEL enum
7028 typedef enum TMDS_CTL1_DATA_SEL {
7040  * TMDS_CTL1_PATTERN_OUT_EN enum
7043 typedef enum TMDS_CTL1_PATTERN_OUT_EN {
7049  * TMDS_CTL2_DATA_INVERT enum
7052 typedef enum TMDS_CTL2_DATA_INVERT {
7058  * TMDS_CTL2_DATA_MODULATION enum
7061 typedef enum TMDS_CTL2_DATA_MODULATION {
7069  * TMDS_CTL2_DATA_SEL enum
7072 typedef enum TMDS_CTL2_DATA_SEL {
7084  * TMDS_CTL2_PATTERN_OUT_EN enum
7087 typedef enum TMDS_CTL2_PATTERN_OUT_EN {
7093  * TMDS_CTL3_DATA_INVERT enum
7096 typedef enum TMDS_CTL3_DATA_INVERT {
7102  * TMDS_CTL3_DATA_MODULATION enum
7105 typedef enum TMDS_CTL3_DATA_MODULATION {
7113  * TMDS_CTL3_DATA_SEL enum
7116 typedef enum TMDS_CTL3_DATA_SEL {
7128  * TMDS_CTL3_PATTERN_OUT_EN enum
7131 typedef enum TMDS_CTL3_PATTERN_OUT_EN {
7137  * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
7140 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
7146  * TMDS_PIXEL_ENCODING enum
7149 typedef enum TMDS_PIXEL_ENCODING {
7155  * TMDS_REG_TEST_OUTPUTA_CNTLA enum
7158 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
7166  * TMDS_REG_TEST_OUTPUTB_CNTLB enum
7169 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
7177  * TMDS_STEREOSYNC_CTL_SEL_REG enum
7180 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
7188  * TMDS_SYNC_PHASE enum
7191 typedef enum TMDS_SYNC_PHASE {
7197  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
7200 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
7206  * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
7209 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
7215  * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
7218 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
7224  * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
7227 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
7233  * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
7236 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
7242  * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
7245 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
7253  * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
7256 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
7262  * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
7265 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
7271  * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
7274 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
7280  * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
7283 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
7289  * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
7292 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
7298  * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
7301 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
7307  * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
7310 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
7320  * DOUT_I2C_ACK enum
7323 typedef enum DOUT_I2C_ACK {
7329  * DOUT_I2C_ARBITRATION_ABORT_XFER enum
7332 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
7338  * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
7341 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
7347  * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
7350 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
7356  * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
7359 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
7367  * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
7370 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
7376  * DOUT_I2C_CONTROL_DBG_REF_SEL enum
7379 typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
7385  * DOUT_I2C_CONTROL_DDC_SELECT enum
7388 typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
7397  * DOUT_I2C_CONTROL_GO enum
7400 typedef enum DOUT_I2C_CONTROL_GO {
7406  * DOUT_I2C_CONTROL_SEND_RESET enum
7409 typedef enum DOUT_I2C_CONTROL_SEND_RESET {
7415  * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum
7418 typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH {
7424  * DOUT_I2C_CONTROL_SOFT_RESET enum
7427 typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
7433  * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
7436 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
7442  * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
7445 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
7453  * DOUT_I2C_DATA_INDEX_WRITE enum
7456 typedef enum DOUT_I2C_DATA_INDEX_WRITE {
7462  * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
7465 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
7471  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
7474 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
7480  * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
7483 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
7489  * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
7492 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
7498  * DOUT_I2C_DDC_SPEED_THRESHOLD enum
7501 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
7509  * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
7512 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
7518  * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
7521 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
7527  * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
7530 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
7540  * CLOCK_GATING_EN enum
7543 typedef enum CLOCK_GATING_EN {
7549  * DAC_MUX_SELECT enum
7552 typedef enum DAC_MUX_SELECT {
7558  * DIOMEM_PWR_DIS_CTRL enum
7561 typedef enum DIOMEM_PWR_DIS_CTRL {
7567  * DIOMEM_PWR_FORCE_CTRL enum
7570 typedef enum DIOMEM_PWR_FORCE_CTRL {
7578  * DIOMEM_PWR_FORCE_CTRL2 enum
7581 typedef enum DIOMEM_PWR_FORCE_CTRL2 {
7587  * DIOMEM_PWR_SEL_CTRL enum
7590 typedef enum DIOMEM_PWR_SEL_CTRL {
7597  * DIOMEM_PWR_SEL_CTRL2 enum
7600 typedef enum DIOMEM_PWR_SEL_CTRL2 {
7606  * DIO_CLOCK_GATING_DISABLE enum
7609 typedef enum DIO_CLOCK_GATING_DISABLE {
7615  * DIO_DBG_BLOCK_SEL enum
7618 typedef enum DIO_DBG_BLOCK_SEL {
7645  * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum
7648 typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE {
7654  * ENUM_DIO_DCN_ACTIVE_STATUS enum
7657 typedef enum ENUM_DIO_DCN_ACTIVE_STATUS {
7663  * GENERIC_STEREOSYNC_SEL enum
7666 typedef enum GENERIC_STEREOSYNC_SEL {
7675  * PM_ASSERT_RESET enum
7678 typedef enum PM_ASSERT_RESET {
7684  * SOFT_RESET enum
7687 typedef enum SOFT_RESET {
7693  * TMDS_MUX_SELECT enum
7696 typedef enum TMDS_MUX_SELECT {
7708  * DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET enum
7711 typedef enum DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET {
7724  * DME_MEM_POWER_STATE_ENUM enum
7727 typedef enum DME_MEM_POWER_STATE_ENUM {
7735  * DME_MEM_PWR_DIS_CTRL enum
7738 typedef enum DME_MEM_PWR_DIS_CTRL {
7744  * DME_MEM_PWR_FORCE_CTRL enum
7747 typedef enum DME_MEM_PWR_FORCE_CTRL {
7755  * METADATA_HUBP_SEL enum
7758 typedef enum METADATA_HUBP_SEL {
7767  * METADATA_STREAM_TYPE_SEL enum
7770 typedef enum METADATA_STREAM_TYPE_SEL {
7780  * VPG_MEM_PWR_DIS_CTRL enum
7783 typedef enum VPG_MEM_PWR_DIS_CTRL {
7789  * VPG_MEM_PWR_FORCE_CTRL enum
7792 typedef enum VPG_MEM_PWR_FORCE_CTRL {
7802  * AFMT_ACP_TYPE enum
7805 typedef enum AFMT_ACP_TYPE {
7813  * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
7816 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
7836  * AFMT_AUDIO_CRC_CONTROL_CONT enum
7839 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
7845  * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
7848 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
7854  * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
7857 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
7863  * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
7866 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
7872  * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
7875 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
7881  * AFMT_AUDIO_SRC_CONTROL_SELECT enum
7884 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
7894  * AFMT_HDMI_AUDIO_SEND_MAX_PACKETS enum
7897 typedef enum AFMT_HDMI_AUDIO_SEND_MAX_PACKETS {
7903  * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
7906 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
7912  * AFMT_INTERRUPT_STATUS_CHG_MASK enum
7915 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
7921  * AFMT_MEM_PWR_DIS_CTRL enum
7924 typedef enum AFMT_MEM_PWR_DIS_CTRL {
7930  * AFMT_MEM_PWR_FORCE_CTRL enum
7933 typedef enum AFMT_MEM_PWR_FORCE_CTRL {
7941  * AFMT_RAMP_CONTROL0_SIGN enum
7944 typedef enum AFMT_RAMP_CONTROL0_SIGN {
7950  * AFMT_VBI_PACKET_CONTROL_ACP_SOURCE enum
7953 typedef enum AFMT_VBI_PACKET_CONTROL_ACP_SOURCE {
7959  * AUDIO_LAYOUT_SELECT enum
7962 typedef enum AUDIO_LAYOUT_SELECT {
7972  * DCOH_TEST_CLOCK_MUX_SELECT_ENUM enum
7975 typedef enum DCOH_TEST_CLOCK_MUX_SELECT_ENUM {
8010  * DCOH_TOP_CLOCK_GATING_DISABLE_ENUM enum
8013 typedef enum DCOH_TOP_CLOCK_GATING_DISABLE_ENUM {
8019  * DCOH_TOP_ENABLE_ENUM enum
8022 typedef enum DCOH_TOP_ENABLE_ENUM {
8032  * PHY_MUX_ENABLE_ENUM enum
8035 typedef enum PHY_MUX_ENABLE_ENUM {
8045  * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
8048 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
8056  * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
8059 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
8065  * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
8068 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
8074  * DP_AUX_ARB_STATUS enum
8077 typedef enum DP_AUX_ARB_STATUS {
8086  * DP_AUX_CONTROL_HPD_SEL enum
8089 typedef enum DP_AUX_CONTROL_HPD_SEL {
8098  * DP_AUX_CONTROL_TEST_MODE enum
8101 typedef enum DP_AUX_CONTROL_TEST_MODE {
8107  * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
8110 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
8116  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
8119 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
8125  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
8128 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
8134  * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
8137 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
8143  * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
8146 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
8154  * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
8157 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
8165  * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
8168 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
8180  * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
8183 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
8195  * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
8198 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
8210  * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
8213 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
8223  * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
8226 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
8234  * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
8237 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
8243  * DP_AUX_ERR_OCCURRED_ACK enum
8246 typedef enum DP_AUX_ERR_OCCURRED_ACK {
8252  * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
8255 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
8261  * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
8264 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
8272  * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
8275 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
8283  * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
8286 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
8294  * DP_AUX_INT_ACK enum
8297 typedef enum DP_AUX_INT_ACK {
8303  * DP_AUX_LS_UPDATE_ACK enum
8306 typedef enum DP_AUX_LS_UPDATE_ACK {
8312  * DP_AUX_PHY_WAKE_PRIORITY enum
8315 typedef enum DP_AUX_PHY_WAKE_PRIORITY {
8321  * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
8324 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
8330  * DP_AUX_RESET enum
8333 typedef enum DP_AUX_RESET {
8339  * DP_AUX_RESET_DONE enum
8342 typedef enum DP_AUX_RESET_DONE {
8348  * DP_AUX_RX_TIMEOUT_LEN_MUL enum
8351 typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL {
8359  * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
8362 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
8368  * DP_AUX_SW_CONTROL_SW_GO enum
8371 typedef enum DP_AUX_SW_CONTROL_SW_GO {
8377  * DP_AUX_TX_PRECHARGE_LEN_MUL enum
8380 typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL {
8392  * HPD_INT_CONTROL_ACK enum
8395 typedef enum HPD_INT_CONTROL_ACK {
8401  * HPD_INT_CONTROL_POLARITY enum
8404 typedef enum HPD_INT_CONTROL_POLARITY {
8410  * HPD_INT_CONTROL_RX_INT_ACK enum
8413 typedef enum HPD_INT_CONTROL_RX_INT_ACK {
8423  * HPO_TOP_CLOCK_GATING_DISABLE enum
8426 typedef enum HPO_TOP_CLOCK_GATING_DISABLE {
8432  * HPO_TOP_TEST_CLK_SEL enum
8435 typedef enum HPO_TOP_TEST_CLK_SEL {
8455  * DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET enum
8458 typedef enum DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET {
8471  * DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum
8474 typedef enum DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR {
8481  * DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum
8484 typedef enum DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT {
8490  * DP_STREAM_ENC_READ_CLOCK_CONTROL enum
8493 typedef enum DP_STREAM_ENC_READ_CLOCK_CONTROL {
8499  * DP_STREAM_ENC_RESET_CONTROL enum
8502 typedef enum DP_STREAM_ENC_RESET_CONTROL {
8508  * DP_STREAM_ENC_STREAM_ACTIVE enum
8511 typedef enum DP_STREAM_ENC_STREAM_ACTIVE {
8521  * ENUM_DP_SYM32_ENC_AUDIO_MUTE enum
8524 typedef enum ENUM_DP_SYM32_ENC_AUDIO_MUTE {
8530  * ENUM_DP_SYM32_ENC_CONTINUOUS_MODE enum
8533 typedef enum ENUM_DP_SYM32_ENC_CONTINUOUS_MODE {
8539  * ENUM_DP_SYM32_ENC_CRC_VALID enum
8542 typedef enum ENUM_DP_SYM32_ENC_CRC_VALID {
8548  * ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH enum
8551 typedef enum ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH {
8559  * ENUM_DP_SYM32_ENC_ENABLE enum
8562 typedef enum ENUM_DP_SYM32_ENC_ENABLE {
8568  * ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED enum
8571 typedef enum ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED {
8577  * ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION enum
8580 typedef enum ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION {
8586  * ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE enum
8589 typedef enum ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE {
8597  * ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING enum
8600 typedef enum ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING {
8606  * ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM enum
8609 typedef enum ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM {
8617  * ENUM_DP_SYM32_ENC_OVERFLOW_STATUS enum
8620 typedef enum ENUM_DP_SYM32_ENC_OVERFLOW_STATUS {
8626  * ENUM_DP_SYM32_ENC_PENDING enum
8629 typedef enum ENUM_DP_SYM32_ENC_PENDING {
8635  * ENUM_DP_SYM32_ENC_PIXEL_ENCODING enum
8638 typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING {
8646  * ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE enum
8649 typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE {
8655  * ENUM_DP_SYM32_ENC_POWER_STATE_ENUM enum
8658 typedef enum ENUM_DP_SYM32_ENC_POWER_STATE_ENUM {
8666  * ENUM_DP_SYM32_ENC_RESET enum
8669 typedef enum ENUM_DP_SYM32_ENC_RESET {
8675  * ENUM_DP_SYM32_ENC_SDP_PRIORITY enum
8678 typedef enum ENUM_DP_SYM32_ENC_SDP_PRIORITY {
8684  * ENUM_DP_SYM32_ENC_SOF_REFERENCE enum
8687 typedef enum ENUM_DP_SYM32_ENC_SOF_REFERENCE {
8693  * ENUM_DP_SYM32_ENC_VID_STREAM_DEFER enum
8696 typedef enum ENUM_DP_SYM32_ENC_VID_STREAM_DEFER {
8707  * ENUM_DP_DPHY_SYM32_CRC_END_EVENT enum
8710 typedef enum ENUM_DP_DPHY_SYM32_CRC_END_EVENT {
8718  * ENUM_DP_DPHY_SYM32_CRC_START_EVENT enum
8721 typedef enum ENUM_DP_DPHY_SYM32_CRC_START_EVENT {
8730  * ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE enum
8733 typedef enum ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE {
8740  * ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS enum
8743 typedef enum ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS {
8749  * ENUM_DP_DPHY_SYM32_ENABLE enum
8752 typedef enum ENUM_DP_DPHY_SYM32_ENABLE {
8758  * ENUM_DP_DPHY_SYM32_MODE enum
8761 typedef enum ENUM_DP_DPHY_SYM32_MODE {
8769  * ENUM_DP_DPHY_SYM32_NUM_LANES enum
8772 typedef enum ENUM_DP_DPHY_SYM32_NUM_LANES {
8780  * ENUM_DP_DPHY_SYM32_OUTPUT_MODE enum
8783 typedef enum ENUM_DP_DPHY_SYM32_OUTPUT_MODE {
8789  * ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING enum
8792 typedef enum ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING {
8798  * ENUM_DP_DPHY_SYM32_RESET enum
8801 typedef enum ENUM_DP_DPHY_SYM32_RESET {
8807  * ENUM_DP_DPHY_SYM32_RESET_STATUS enum
8810 typedef enum ENUM_DP_DPHY_SYM32_RESET_STATUS {
8816  * ENUM_DP_DPHY_SYM32_SAT_UPDATE enum
8819 typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE {
8826  * ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING enum
8829 typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING {
8836  * ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS enum
8839 typedef enum ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS {
8846  * ENUM_DP_DPHY_SYM32_STATUS enum
8849 typedef enum ENUM_DP_DPHY_SYM32_STATUS {
8855  * ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE enum
8858 typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE {
8865  * ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE enum
8868 typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE {
8874  * ENUM_DP_DPHY_SYM32_TP_PRBS_SEL enum
8877 typedef enum ENUM_DP_DPHY_SYM32_TP_PRBS_SEL {
8887  * ENUM_DP_DPHY_SYM32_TP_SELECT enum
8890 typedef enum ENUM_DP_DPHY_SYM32_TP_SELECT {
8903  * APG_AUDIO_CRC_CONTROL_CH_SEL enum
8906 typedef enum APG_AUDIO_CRC_CONTROL_CH_SEL {
8926  * APG_AUDIO_CRC_CONTROL_CONT enum
8929 typedef enum APG_AUDIO_CRC_CONTROL_CONT {
8935  * APG_DBG_ACP_TYPE enum
8938 typedef enum APG_DBG_ACP_TYPE {
8946  * APG_DBG_AUDIO_DTO_BASE enum
8949 typedef enum APG_DBG_AUDIO_DTO_BASE {
8955  * APG_DBG_AUDIO_DTO_DIV enum
8958 typedef enum APG_DBG_AUDIO_DTO_DIV {
8970  * APG_DBG_AUDIO_DTO_MULTI enum
8973 typedef enum APG_DBG_AUDIO_DTO_MULTI {
8982  * APG_DBG_MUX_SEL enum
8985 typedef enum APG_DBG_MUX_SEL {
8991  * APG_DP_ASP_CHANNEL_COUNT_OVERRIDE enum
8994 typedef enum APG_DP_ASP_CHANNEL_COUNT_OVERRIDE {
9000  * APG_MEM_POWER_STATE enum
9003 typedef enum APG_MEM_POWER_STATE {
9011  * APG_MEM_PWR_DIS_CTRL enum
9014 typedef enum APG_MEM_PWR_DIS_CTRL {
9020  * APG_MEM_PWR_FORCE_CTRL enum
9023 typedef enum APG_MEM_PWR_FORCE_CTRL {
9031  * APG_PACKET_CONTROL_ACP_SOURCE enum
9034 typedef enum APG_PACKET_CONTROL_ACP_SOURCE {
9040  * APG_PACKET_CONTROL_AUDIO_INFO_SOURCE enum
9043 typedef enum APG_PACKET_CONTROL_AUDIO_INFO_SOURCE {
9049  * APG_RAMP_CONTROL_SIGN enum
9052 typedef enum APG_RAMP_CONTROL_SIGN {
9062  * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
9065 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
9075  * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
9078 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
9085  * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
9088 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
9094  * DCIO_DBG_ASYNC_4BIT_SEL enum
9097 typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
9109  * DCIO_DBG_ASYNC_BLOCK_SEL enum
9112 typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
9120  * DCIO_DCRXPHY_SOFT_RESET enum
9123 typedef enum DCIO_DCRXPHY_SOFT_RESET {
9129  * DCIO_DC_GENERICA_SEL enum
9132 typedef enum DCIO_DC_GENERICA_SEL {
9139  * DCIO_DC_GENERICB_SEL enum
9142 typedef enum DCIO_DC_GENERICB_SEL {
9149  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
9152 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
9163  * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
9166 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
9177  * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
9180 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
9191  * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
9194 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
9205  * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
9208 typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
9214  * DCIO_DC_GPU_TIMER_READ_SELECT enum
9217 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
9227  * DCIO_DC_GPU_TIMER_START_POSITION enum
9230 typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
9242  * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
9245 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
9253  * DCIO_DIO_EXT_VSYNC_MASK enum
9256 typedef enum DCIO_DIO_EXT_VSYNC_MASK {
9268  * DCIO_DIO_OTG_EXT_VSYNC_MUX enum
9271 typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX {
9283  * DCIO_DPCS_INTERRUPT_MASK enum
9286 typedef enum DCIO_DPCS_INTERRUPT_MASK {
9292  * DCIO_DPCS_INTERRUPT_TYPE enum
9295 typedef enum DCIO_DPCS_INTERRUPT_TYPE {
9301  * DCIO_GENLK_CLK_GSL_MASK enum
9304 typedef enum DCIO_GENLK_CLK_GSL_MASK {
9311  * DCIO_GENLK_VSYNC_GSL_MASK enum
9314 typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
9321  * DCIO_GSL_SEL enum
9324 typedef enum DCIO_GSL_SEL {
9331  * DCIO_PHY_HPO_ENC_SRC_SEL enum
9334 typedef enum DCIO_PHY_HPO_ENC_SRC_SEL {
9340  * DCIO_SWAPLOCK_A_GSL_MASK enum
9343 typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
9350  * DCIO_SWAPLOCK_B_GSL_MASK enum
9353 typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
9360  * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
9363 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
9371  * DCIO_UNIPHY_IMPCAL_SEL enum
9374 typedef enum DCIO_UNIPHY_IMPCAL_SEL {
9380  * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
9383 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
9389  * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
9392 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
9404  * DCIOCHIP_AUX_ALL_PWR_OK enum
9407 typedef enum DCIOCHIP_AUX_ALL_PWR_OK {
9413  * DCIOCHIP_AUX_CSEL0P9 enum
9416 typedef enum DCIOCHIP_AUX_CSEL0P9 {
9422  * DCIOCHIP_AUX_CSEL1P1 enum
9425 typedef enum DCIOCHIP_AUX_CSEL1P1 {
9431  * DCIOCHIP_AUX_FALLSLEWSEL enum
9434 typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
9442  * DCIOCHIP_AUX_HYS_TUNE enum
9445 typedef enum DCIOCHIP_AUX_HYS_TUNE {
9453  * DCIOCHIP_AUX_RECEIVER_SEL enum
9456 typedef enum DCIOCHIP_AUX_RECEIVER_SEL {
9464  * DCIOCHIP_AUX_RSEL0P9 enum
9467 typedef enum DCIOCHIP_AUX_RSEL0P9 {
9473  * DCIOCHIP_AUX_RSEL1P1 enum
9476 typedef enum DCIOCHIP_AUX_RSEL1P1 {
9482  * DCIOCHIP_AUX_SPIKESEL enum
9485 typedef enum DCIOCHIP_AUX_SPIKESEL {
9491  * DCIOCHIP_AUX_VOD_TUNE enum
9494 typedef enum DCIOCHIP_AUX_VOD_TUNE {
9502  * DCIOCHIP_GPIO_MASK_EN enum
9505 typedef enum DCIOCHIP_GPIO_MASK_EN {
9511  * DCIOCHIP_HPD_SEL enum
9514 typedef enum DCIOCHIP_HPD_SEL {
9520  * DCIOCHIP_I2C_COMPSEL enum
9523 typedef enum DCIOCHIP_I2C_COMPSEL {
9529  * DCIOCHIP_I2C_FALLSLEWSEL enum
9532 typedef enum DCIOCHIP_I2C_FALLSLEWSEL {
9540  * DCIOCHIP_I2C_RECEIVER_SEL enum
9543 typedef enum DCIOCHIP_I2C_RECEIVER_SEL {
9551  * DCIOCHIP_I2C_VPH_1V2_EN enum
9554 typedef enum DCIOCHIP_I2C_VPH_1V2_EN {
9560  * DCIOCHIP_INVERT enum
9563 typedef enum DCIOCHIP_INVERT {
9569  * DCIOCHIP_MASK enum
9572 typedef enum DCIOCHIP_MASK {
9578  * DCIOCHIP_PAD_MODE enum
9581 typedef enum DCIOCHIP_PAD_MODE {
9587  * DCIOCHIP_PD_EN enum
9590 typedef enum DCIOCHIP_PD_EN {
9596  * DCIOCHIP_REF_27_SRC_SEL enum
9599 typedef enum DCIOCHIP_REF_27_SRC_SEL {
9611  * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
9614 typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
9620  * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN enum
9623 typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN {
9629  * PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
9632 typedef enum PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
9640  * PWRSEQ_BL_PWM_CNTL_BL_PWM_EN enum
9643 typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_EN {
9649  * PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
9652 typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
9658  * PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
9661 typedef enum PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
9667  * PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
9670 typedef enum PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
9676  * PWRSEQ_BL_PWM_GRP1_REG_LOCK enum
9679 typedef enum PWRSEQ_BL_PWM_GRP1_REG_LOCK {
9685  * PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
9688 typedef enum PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
9694  * PWRSEQ_GPIO_MASK_EN enum
9697 typedef enum PWRSEQ_GPIO_MASK_EN {
9703  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON enum
9706 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON {
9712  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL enum
9715 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL {
9721  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON enum
9724 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON {
9730  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL enum
9733 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL {
9739  * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL enum
9742 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL {
9748  * PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE enum
9751 typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE {
9757  * PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN enum
9760 typedef enum PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN {
9770  * AZ_CORB_SIZE enum
9773 typedef enum AZ_CORB_SIZE {
9781  * AZ_GLOBAL_CAPABILITIES enum
9784 typedef enum AZ_GLOBAL_CAPABILITIES {
9790  * AZ_RIRB_SIZE enum
9793 typedef enum AZ_RIRB_SIZE {
9801  * AZ_RIRB_WRITE_POINTER_RESET enum
9804 typedef enum AZ_RIRB_WRITE_POINTER_RESET {
9810  * AZ_STATE_CHANGE_STATUS enum
9813 typedef enum AZ_STATE_CHANGE_STATUS {
9819  * CORB_READ_POINTER_RESET enum
9822 typedef enum CORB_READ_POINTER_RESET {
9828  * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
9831 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
9837  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
9840 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
9846  * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
9849 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
9855  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
9858 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
9864  * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
9867 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
9873  * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
9876 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
9882  * GLOBAL_CONTROL_CONTROLLER_RESET enum
9885 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
9891  * GLOBAL_CONTROL_FLUSH_CONTROL enum
9894 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
9900  * GLOBAL_STATUS_FLUSH_STATUS enum
9903 typedef enum GLOBAL_STATUS_FLUSH_STATUS {
9909  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
9912 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
9918  * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
9921 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
9927  * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
9930 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
9936  * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
9939 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
9945  * STREAM_0_SYNCHRONIZATION enum
9948 typedef enum STREAM_0_SYNCHRONIZATION {
9954  * STREAM_10_SYNCHRONIZATION enum
9957 typedef enum STREAM_10_SYNCHRONIZATION {
9963  * STREAM_11_SYNCHRONIZATION enum
9966 typedef enum STREAM_11_SYNCHRONIZATION {
9972  * STREAM_12_SYNCHRONIZATION enum
9975 typedef enum STREAM_12_SYNCHRONIZATION {
9981  * STREAM_13_SYNCHRONIZATION enum
9984 typedef enum STREAM_13_SYNCHRONIZATION {
9990  * STREAM_14_SYNCHRONIZATION enum
9993 typedef enum STREAM_14_SYNCHRONIZATION {
9999  * STREAM_15_SYNCHRONIZATION enum
10002 typedef enum STREAM_15_SYNCHRONIZATION {
10008  * STREAM_1_SYNCHRONIZATION enum
10011 typedef enum STREAM_1_SYNCHRONIZATION {
10017  * STREAM_2_SYNCHRONIZATION enum
10020 typedef enum STREAM_2_SYNCHRONIZATION {
10026  * STREAM_3_SYNCHRONIZATION enum
10029 typedef enum STREAM_3_SYNCHRONIZATION {
10035  * STREAM_4_SYNCHRONIZATION enum
10038 typedef enum STREAM_4_SYNCHRONIZATION {
10044  * STREAM_5_SYNCHRONIZATION enum
10047 typedef enum STREAM_5_SYNCHRONIZATION {
10053  * STREAM_6_SYNCHRONIZATION enum
10056 typedef enum STREAM_6_SYNCHRONIZATION {
10062  * STREAM_7_SYNCHRONIZATION enum
10065 typedef enum STREAM_7_SYNCHRONIZATION {
10071  * STREAM_8_SYNCHRONIZATION enum
10074 typedef enum STREAM_8_SYNCHRONIZATION {
10080  * STREAM_9_SYNCHRONIZATION enum
10083 typedef enum STREAM_9_SYNCHRONIZATION {
10093  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10096 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10106  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10109 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10122  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10125 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10137  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10140 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10149  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10152 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10158  * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10161 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10167  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10170 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10176  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10179 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10185  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10188 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10194  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10197 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10203  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10206 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10212  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10215 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10221  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10224 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10230  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10233 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10239  * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10242 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10248  * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum
10251 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE {
10271  * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10274 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10280  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10283 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10289  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10292 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10298  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10301 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10307  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10310 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10316  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10319 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10325  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10328 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10334  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10337 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10343  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10346 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10352  * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10355 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10361  * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10364 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10370  * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10373 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10383  * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10386 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10392  * MEM_PWR_DIS_CTRL enum
10395 typedef enum MEM_PWR_DIS_CTRL {
10401  * MEM_PWR_FORCE_CTRL enum
10404 typedef enum MEM_PWR_FORCE_CTRL {
10412  * MEM_PWR_FORCE_CTRL2 enum
10415 typedef enum MEM_PWR_FORCE_CTRL2 {
10421  * MEM_PWR_SEL_CTRL enum
10424 typedef enum MEM_PWR_SEL_CTRL {
10431  * MEM_PWR_SEL_CTRL2 enum
10434 typedef enum MEM_PWR_SEL_CTRL2 {
10444  * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
10447 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
10459  * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
10462 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
10478  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10481 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10491  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10494 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10507  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10510 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10522  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10525 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10534  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10537 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10543  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10546 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10552  * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10555 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10561  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
10564 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
10570  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10573 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10579  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
10582 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
10588  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10591 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10597  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
10600 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
10606  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10609 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10615  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
10618 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
10624  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10627 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10633  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10636 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10642  * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
10645 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
10655  * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
10658 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
10668  * AZ_LATENCY_COUNTER_CONTROL enum
10671 typedef enum AZ_LATENCY_COUNTER_CONTROL {
10681  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
10684 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
10690  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
10693 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
10699  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
10702 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
10708  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
10711 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
10717  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
10720 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
10726  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
10729 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
10735  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
10738 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
10744  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
10747 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
10753  * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
10756 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
10762  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
10765 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
10775  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
10778 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
10798  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
10801 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
10813  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
10816 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
10825  * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
10828 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
10838  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10841 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
10847  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
10850 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITI…
10856  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10859 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10865  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10868 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10874  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
10877 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
10883  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10886 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10892  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10895 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10901  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10904 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
10910  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10913 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10919  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10922 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10928  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10931 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10937  * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10940 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10954 … AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10957 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
10963  * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10966 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10972  * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
10975 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
10981  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10984 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10990  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10993 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10999  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11002 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11008  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11011 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11017  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11020 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11026  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11029 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11035  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11038 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11044  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11047 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11053  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11056 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11062  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11065 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11079  * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11082 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILIT…
11088  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11091 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11097  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
11100 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
11106  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
11109 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
11115  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
11118 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
11124  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
11127 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
11133  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
11136 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
11142  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
11145 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
11151  * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
11154 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
11164 …ALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11167 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETE…
11173 …AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
11176 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPA…
11182  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11185 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11191  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11194 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11200  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
11203 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
11209  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11212 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PR…
11218  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11221 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11227  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11230 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_P…
11236  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11239 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11245  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11248 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11254  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11257 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11263  * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11266 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11280 …A_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11283 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPON…
11289  * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
11292 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
11298  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11301 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
11307  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11310 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11316  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11319 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11325  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11328 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11334  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11337 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11343  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11346 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
11352  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11355 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11361  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11364 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11370  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11373 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11379  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11382 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11396 … AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11399 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
11405  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11408 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11414  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
11417 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
11423  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
11426 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
11432  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
11435 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
11441  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
11444 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
11450  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
11453 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
11459  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
11462 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
11468  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
11471 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
11477  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
11480 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
11486  * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
11489 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
11499  * DSCC_BITS_PER_COMPONENT_ENUM enum
11502 typedef enum DSCC_BITS_PER_COMPONENT_ENUM {
11509  * DSCC_DSC_VERSION_MAJOR_ENUM enum
11512 typedef enum DSCC_DSC_VERSION_MAJOR_ENUM {
11517  * DSCC_DSC_VERSION_MINOR_ENUM enum
11520 typedef enum DSCC_DSC_VERSION_MINOR_ENUM {
11526  * DSCC_ENABLE_ENUM enum
11529 typedef enum DSCC_ENABLE_ENUM {
11535  * DSCC_ICH_RESET_ENUM enum
11538 typedef enum DSCC_ICH_RESET_ENUM {
11546  * DSCC_LINEBUF_DEPTH_ENUM enum
11549 typedef enum DSCC_LINEBUF_DEPTH_ENUM {
11559  * DSCC_MEM_PWR_DIS_ENUM enum
11562 typedef enum DSCC_MEM_PWR_DIS_ENUM {
11568  * DSCC_MEM_PWR_FORCE_ENUM enum
11571 typedef enum DSCC_MEM_PWR_FORCE_ENUM {
11579  * POWER_STATE_ENUM enum
11582 typedef enum POWER_STATE_ENUM {
11594  * DSCCIF_BITS_PER_COMPONENT_ENUM enum
11597 typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM {
11604  * DSCCIF_ENABLE_ENUM enum
11607 typedef enum DSCCIF_ENABLE_ENUM {
11613  * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum
11616 typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM {
11629  * CLOCK_GATING_DISABLE_ENUM enum
11632 typedef enum CLOCK_GATING_DISABLE_ENUM {
11638  * ENABLE_ENUM enum
11641 typedef enum ENABLE_ENUM {
11647  * TEST_CLOCK_MUX_SELECT_ENUM enum
11650 typedef enum TEST_CLOCK_MUX_SELECT_ENUM {
11665  * DWB_CRC_CONT_EN_ENUM enum
11668 typedef enum DWB_CRC_CONT_EN_ENUM {
11674  * DWB_CRC_SRC_SEL_ENUM enum
11677 typedef enum DWB_CRC_SRC_SEL_ENUM {
11684  * DWB_DATA_OVERFLOW_INT_TYPE_ENUM enum
11687 typedef enum DWB_DATA_OVERFLOW_INT_TYPE_ENUM {
11693  * DWB_DATA_OVERFLOW_TYPE_ENUM enum
11696 typedef enum DWB_DATA_OVERFLOW_TYPE_ENUM {
11704  * DWB_DEBUG_SEL_ENUM enum
11707 typedef enum DWB_DEBUG_SEL_ENUM {
11715  * DWB_MEM_PWR_FORCE_ENUM enum
11718 typedef enum DWB_MEM_PWR_FORCE_ENUM {
11726  * DWB_MEM_PWR_STATE_ENUM enum
11729 typedef enum DWB_MEM_PWR_STATE_ENUM {
11737  * DWB_TEST_CLK_SEL_ENUM enum
11740 typedef enum DWB_TEST_CLK_SEL_ENUM {
11747  * FC_EYE_SELECTION_ENUM enum
11750 typedef enum FC_EYE_SELECTION_ENUM {
11757  * FC_FRAME_CAPTURE_RATE_ENUM enum
11760 typedef enum FC_FRAME_CAPTURE_RATE_ENUM {
11768  * FC_STEREO_EYE_POLARITY_ENUM enum
11771 typedef enum FC_STEREO_EYE_POLARITY_ENUM {
11781  * DWB_GAMUT_REMAP_COEF_FORMAT_ENUM enum
11784 typedef enum DWB_GAMUT_REMAP_COEF_FORMAT_ENUM {
11790  * DWB_GAMUT_REMAP_MODE_ENUM enum
11793 typedef enum DWB_GAMUT_REMAP_MODE_ENUM {
11801  * DWB_LUT_NUM_SEG enum
11804 typedef enum DWB_LUT_NUM_SEG {
11816  * DWB_OGAM_LUT_CONFIG_MODE_ENUM enum
11819 typedef enum DWB_OGAM_LUT_CONFIG_MODE_ENUM {
11825  * DWB_OGAM_LUT_HOST_SEL_ENUM enum
11828 typedef enum DWB_OGAM_LUT_HOST_SEL_ENUM {
11834  * DWB_OGAM_LUT_READ_COLOR_SEL_ENUM enum
11837 typedef enum DWB_OGAM_LUT_READ_COLOR_SEL_ENUM {
11845  * DWB_OGAM_LUT_READ_DBG_ENUM enum
11848 typedef enum DWB_OGAM_LUT_READ_DBG_ENUM {
11854  * DWB_OGAM_MODE_ENUM enum
11857 typedef enum DWB_OGAM_MODE_ENUM {
11864  * DWB_OGAM_PWL_DISABLE_ENUM enum
11867 typedef enum DWB_OGAM_PWL_DISABLE_ENUM {
11873  * DWB_OGAM_SELECT_ENUM enum
11876 typedef enum DWB_OGAM_SELECT_ENUM {
11886  * RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN enum
11889 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN {
11895  * RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON enum
11898 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON {
11904  * RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN enum
11907 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN {
11913  * RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS enum
11916 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS {
11922  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum
11925 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON {
11931  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum
11934 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN {
11940  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum
11943 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS {
11949  * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS enum
11952 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS {
11958  * RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON enum
11961 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON {
11967  * RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN enum
11970 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN {
11976  * RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS enum
11979 typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS {
11985  * RDPCSTX_CLOCK_CNTL_TX_CLK_EN enum
11988 typedef enum RDPCSTX_CLOCK_CNTL_TX_CLK_EN {
11994  * RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET enum
11997 typedef enum RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET {
12003  * RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET enum
12006 typedef enum RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET {
12012  * RDPCSTX_CNTL_RDPCS_TX_FIFO_EN enum
12015 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_EN {
12021  * RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN enum
12024 typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN {
12030  * RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET enum
12033 typedef enum RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET {
12039  * RDPCSTX_FIFO_EMPTY enum
12042 typedef enum RDPCSTX_FIFO_EMPTY {
12048  * RDPCSTX_FIFO_FULL enum
12051 typedef enum RDPCSTX_FIFO_FULL {
12057  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum
12060 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE {
12066  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum
12069 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK {
12075  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum
12078 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE {
12084  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum
12087 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK {
12093  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum
12096 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK {
12102  * RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK enum
12105 typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK {
12111  * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum
12114 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL {
12120  * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum
12123 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL {
12129  * RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum
12132 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE {
12144  * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum
12147 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE {
12153  * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum
12156 typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE {
12162  * RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum
12165 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV {
12174  * RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum
12177 typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV {
12185  * RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum
12188 typedef enum RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV {
12200  * RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum
12203 typedef enum RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL {
12215  * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum
12218 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT {
12224  * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum
12227 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE {
12234  * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum
12237 typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH {
12245  * RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum
12248 typedef enum RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE {
12256  * RDPCSTX_PHY_REF_ALT_CLK_EN enum
12259 typedef enum RDPCSTX_PHY_REF_ALT_CLK_EN {
12265  * RDPCSTX_TX_FIFO_DISABLED_MASK enum
12268 typedef enum RDPCSTX_TX_FIFO_DISABLED_MASK {
12274  * RDPCS_DBG_OCLA_SEL enum
12277 typedef enum RDPCS_DBG_OCLA_SEL {
12289  * RDPCS_TEST_CLK_SEL enum
12292 typedef enum RDPCS_TEST_CLK_SEL {
12314  * RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB enum
12317 typedef enum RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB {
12323  * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum
12326 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE {
12334  * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum
12337 typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE {
12345  * RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK enum
12348 typedef enum RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK {
12358  * RLC_DOORBELL_MODE enum
12361 typedef enum RLC_DOORBELL_MODE {
12369  * RLC_PERFCOUNTER_SEL enum
12372 typedef enum RLC_PERFCOUNTER_SEL {
12383  * RLC_PERFMON_STATE enum
12386 typedef enum RLC_PERFMON_STATE {
12398  * RSPM_CMD enum
12401 typedef enum RSPM_CMD {
12420  * CSCNTL_TYPE enum
12423 typedef enum CSCNTL_TYPE {
12431  * CSDATA_TYPE enum
12434 typedef enum CSDATA_TYPE {
12482  * GE1_PERFCOUNT_SELECT enum
12485 typedef enum GE1_PERFCOUNT_SELECT {
12529  * GE2_DIST_PERFCOUNT_SELECT enum
12532 typedef enum GE2_DIST_PERFCOUNT_SELECT {
12637  * GE2_SE_PERFCOUNT_SELECT enum
12640 typedef enum GE2_SE_PERFCOUNT_SELECT {
12732  * VGT_DETECT_ONE enum
12735 typedef enum VGT_DETECT_ONE {
12741  * VGT_DETECT_ZERO enum
12744 typedef enum VGT_DETECT_ZERO {
12750  * VGT_DIST_MODE enum
12753 typedef enum VGT_DIST_MODE {
12761  * VGT_DI_INDEX_SIZE enum
12764 typedef enum VGT_DI_INDEX_SIZE {
12771  * VGT_DI_PRIM_TYPE enum
12774 typedef enum VGT_DI_PRIM_TYPE {
12800  * VGT_DI_SOURCE_SELECT enum
12803 typedef enum VGT_DI_SOURCE_SELECT {
12811  * VGT_DMA_BUF_TYPE enum
12814 typedef enum VGT_DMA_BUF_TYPE {
12822  * VGT_DMA_SWAP_MODE enum
12825 typedef enum VGT_DMA_SWAP_MODE {
12833  * VGT_EVENT_TYPE enum
12836 typedef enum VGT_EVENT_TYPE {
12904  * VGT_GROUP_CONV_SEL enum
12907 typedef enum VGT_GROUP_CONV_SEL {
12920  * VGT_GS_MODE_TYPE enum
12923 typedef enum VGT_GS_MODE_TYPE {
12933  * VGT_GS_OUTPRIM_TYPE enum
12936 typedef enum VGT_GS_OUTPRIM_TYPE {
12945  * VGT_INDEX_TYPE_MODE enum
12948 typedef enum VGT_INDEX_TYPE_MODE {
12955  * VGT_OUTPATH_SELECT enum
12958 typedef enum VGT_OUTPATH_SELECT {
12969  * VGT_OUT_PRIM_TYPE enum
12972 typedef enum VGT_OUT_PRIM_TYPE {
12987  * VGT_RDREQ_POLICY enum
12990 typedef enum VGT_RDREQ_POLICY {
12997  * VGT_SPEC_DATA_READ enum
13000 typedef enum VGT_SPEC_DATA_READ {
13007  * VGT_STAGES_GS_EN enum
13010 typedef enum VGT_STAGES_GS_EN {
13016  * VGT_STAGES_HS_EN enum
13019 typedef enum VGT_STAGES_HS_EN {
13025  * VGT_TEMPORAL enum
13028 typedef enum VGT_TEMPORAL {
13036  * VGT_TESS_PARTITION enum
13039 typedef enum VGT_TESS_PARTITION {
13047  * VGT_TESS_TOPOLOGY enum
13050 typedef enum VGT_TESS_TOPOLOGY {
13058  * VGT_TESS_TYPE enum
13061 typedef enum VGT_TESS_TYPE {
13068  * WD_IA_DRAW_REG_XFER enum
13071 typedef enum WD_IA_DRAW_REG_XFER {
13097  * WD_IA_DRAW_SOURCE enum
13100 typedef enum WD_IA_DRAW_SOURCE {
13108  * WD_IA_DRAW_TYPE enum
13111 typedef enum WD_IA_DRAW_TYPE {
13133  * CHA_PERF_SEL enum
13136 typedef enum CHA_PERF_SEL {
13172  * CHC_PERF_SEL enum
13175 typedef enum CHC_PERF_SEL {
13227  * GRBM_PERF_SEL enum
13230 typedef enum GRBM_PERF_SEL {
13273  * CPC_LATENCY_STATS_SEL enum
13276 typedef enum CPC_LATENCY_STATS_SEL {
13289  * CPC_PERFCOUNT_SEL enum
13292 typedef enum CPC_PERFCOUNT_SEL {
13350  * CPF_LATENCY_STATS_SEL enum
13353 typedef enum CPF_LATENCY_STATS_SEL {
13369  * CPF_PERFCOUNTWINDOW_SEL enum
13372 typedef enum CPF_PERFCOUNTWINDOW_SEL {
13381  * CPF_PERFCOUNT_SEL enum
13384 typedef enum CPF_PERFCOUNT_SEL {
13429  * CPF_SCRATCH_REG_ATOMIC_OP enum
13432 typedef enum CPF_SCRATCH_REG_ATOMIC_OP {
13444  * CPG_LATENCY_STATS_SEL enum
13447 typedef enum CPG_LATENCY_STATS_SEL {
13469  * CPG_PERFCOUNTWINDOW_SEL enum
13472 typedef enum CPG_PERFCOUNTWINDOW_SEL {
13507  * CPG_PERFCOUNT_SEL enum
13510 typedef enum CPG_PERFCOUNT_SEL {
13601  * CP_ALPHA_TAG_RAM_SEL enum
13604 typedef enum CP_ALPHA_TAG_RAM_SEL {
13612  * CP_DDID_CNTL_MODE enum
13615 typedef enum CP_DDID_CNTL_MODE {
13621  * CP_DDID_CNTL_SIZE enum
13624 typedef enum CP_DDID_CNTL_SIZE {
13630  * CP_DDID_CNTL_VMID_SEL enum
13633 typedef enum CP_DDID_CNTL_VMID_SEL {
13639  * CP_ME_ID enum
13642 typedef enum CP_ME_ID {
13650  * CP_PIPE_ID enum
13653 typedef enum CP_PIPE_ID {
13661  * CP_RING_ID enum
13664 typedef enum CP_RING_ID {
13741  * GCRPerfSel enum
13744 typedef enum GCRPerfSel {
13907  * GC_EA_CPWD_PERFCOUNT_SEL enum
13910 typedef enum GC_EA_CPWD_PERFCOUNT_SEL {
14016  * GCVML2_SPM_PERF_SEL enum
14019 typedef enum GCVML2_SPM_PERF_SEL {
14118  * GCUTCL2_PERF_SEL enum
14121 typedef enum GCUTCL2_PERF_SEL {
14162  * GCVML2_PERF_SEL enum
14165 typedef enum GCVML2_PERF_SEL {
14264  * BlendOp enum
14267 typedef enum BlendOp {
14290  * BlendOpt enum
14293 typedef enum BlendOpt {
14305  * CBMode enum
14308 typedef enum CBMode {
14317  * CBPerfClearFilterSel enum
14320 typedef enum CBPerfClearFilterSel {
14326  * CBPerfOpFilterSel enum
14329 typedef enum CBPerfOpFilterSel {
14339  * CBPerfSel enum
14342 typedef enum CBPerfSel {
14498  * CombFunc enum
14501 typedef enum CombFunc {
14510  * MemArbMode enum
14513 typedef enum MemArbMode {
14525  * PH_PERFCNT_SEL enum
14528 typedef enum PH_PERFCNT_SEL {
15556  * PhSPIstatusMode enum
15559 typedef enum PhSPIstatusMode {
15570  * BinEventCntl enum
15573 typedef enum BinEventCntl {
15581  * BinMapMode enum
15584 typedef enum BinMapMode {
15591  * BinSizeExtend enum
15594 typedef enum BinSizeExtend {
15603  * BinningMode enum
15606 typedef enum BinningMode {
15614  * PkrMap enum
15617 typedef enum PkrMap {
15625  * PkrXsel enum
15628 typedef enum PkrXsel {
15636  * PkrXsel2 enum
15639 typedef enum PkrXsel2 {
15647  * PkrYsel enum
15650 typedef enum PkrYsel {
15658  * RbMap enum
15661 typedef enum RbMap {
15669  * RbXsel enum
15672 typedef enum RbXsel {
15678  * RbXsel2 enum
15681 typedef enum RbXsel2 {
15689  * RbYsel enum
15692 typedef enum RbYsel {
15698  * SC_PERFCNT_SEL enum
15701 typedef enum SC_PERFCNT_SEL {
16367  * ScMap enum
16370 typedef enum ScMap {
16378  * ScUncertaintyRegionMode enum
16381 typedef enum ScUncertaintyRegionMode {
16388  * ScUncertaintyRegionMult enum
16391 typedef enum ScUncertaintyRegionMult {
16399  * ScXsel enum
16402 typedef enum ScXsel {
16410  * ScYsel enum
16413 typedef enum ScYsel {
16421  * SeMap enum
16424 typedef enum SeMap {
16432  * SePairMap enum
16435 typedef enum SePairMap {
16443  * SePairXsel enum
16446 typedef enum SePairXsel {
16454  * SePairYsel enum
16457 typedef enum SePairYsel {
16465  * SeXsel enum
16468 typedef enum SeXsel {
16476  * SeYsel enum
16479 typedef enum SeYsel {
16487  * VRSCombinerModeSC enum
16490 typedef enum VRSCombinerModeSC {
16499  * VRSrate enum
16502 typedef enum VRSrate {
16526  * TC_EA_CID enum
16529 typedef enum TC_EA_CID {
16549  * TC_NACKS enum
16552 typedef enum TC_NACKS {
16560  * TC_OP enum
16563 typedef enum TC_OP {
16695  * TC_OP_MASKS enum
16698 typedef enum TC_OP_MASKS {
16709  * CLKGATE_BASE_MODE enum
16712 typedef enum CLKGATE_BASE_MODE {
16718  * CLKGATE_SM_MODE enum
16721 typedef enum CLKGATE_SM_MODE {
16730  * CovToShaderSel enum
16733 typedef enum CovToShaderSel {
16741  * PC_PERFCNT_SEL enum
16744 typedef enum PC_PERFCNT_SEL {
16913  * SPI_FOG_MODE enum
16916 typedef enum SPI_FOG_MODE {
16924  * SPI_LB_WAVES_SELECT enum
16927 typedef enum SPI_LB_WAVES_SELECT {
16935  * SPI_PERFCNT_SEL enum
16938 typedef enum SPI_PERFCNT_SEL {
17226  * SPI_PNT_SPRITE_OVERRIDE enum
17229 typedef enum SPI_PNT_SPRITE_OVERRIDE {
17238  * SPI_PS_LDS_GROUP_SIZE enum
17241 typedef enum SPI_PS_LDS_GROUP_SIZE {
17248  * SPI_SAMPLE_CNTL enum
17251 typedef enum SPI_SAMPLE_CNTL {
17259  * SPI_SHADER_EX_FORMAT enum
17262 typedef enum SPI_SHADER_EX_FORMAT {
17276  * SPI_SHADER_FORMAT enum
17279 typedef enum SPI_SHADER_FORMAT {
17292  * SH_MEM_ADDRESS_MODE enum
17295 typedef enum SH_MEM_ADDRESS_MODE {
17301  * SH_MEM_ALIGNMENT_MODE enum
17304 typedef enum SH_MEM_ALIGNMENT_MODE {
17312  * SQG_PERF_SEL enum
17315 typedef enum SQG_PERF_SEL {
17366  * SQ_CAC_POWER_SEL enum
17369 typedef enum SQ_CAC_POWER_SEL {
17382  * SQ_EDC_INFO_SOURCE enum
17385 typedef enum SQ_EDC_INFO_SOURCE {
17396  * SQ_IBUF_ST enum
17399 typedef enum SQ_IBUF_ST {
17411  * SQ_IMG_FILTER_TYPE enum
17414 typedef enum SQ_IMG_FILTER_TYPE {
17421  * SQ_IND_CMD_CMD enum
17424 typedef enum SQ_IND_CMD_CMD {
17437  * SQ_IND_CMD_MODE enum
17440 typedef enum SQ_IND_CMD_MODE {
17449  * SQ_INST_STR_ST enum
17452 typedef enum SQ_INST_STR_ST {
17462  * SQ_INST_TYPE enum
17465 typedef enum SQ_INST_TYPE {
17485  * SQ_LLC_CTL enum
17488 typedef enum SQ_LLC_CTL {
17496  * SQ_NO_INST_ISSUE enum
17499 typedef enum SQ_NO_INST_ISSUE {
17511  * SQ_OOB_SELECT enum
17514 typedef enum SQ_OOB_SELECT {
17522  * SQ_PERF_SEL enum
17525 typedef enum SQ_PERF_SEL {
17911  * SQ_ROUND_MODE enum
17914 typedef enum SQ_ROUND_MODE {
17922  * SQ_RSRC_BUF_TYPE enum
17925 typedef enum SQ_RSRC_BUF_TYPE {
17933  * SQ_RSRC_FLAT_TYPE enum
17936 typedef enum SQ_RSRC_FLAT_TYPE {
17944  * SQ_RSRC_IMG_TYPE enum
17947 typedef enum SQ_RSRC_IMG_TYPE {
17967  * SQ_SEL_XYZW01 enum
17970 typedef enum SQ_SEL_XYZW01 {
17982  * SQ_TEX_ANISO_RATIO enum
17985 typedef enum SQ_TEX_ANISO_RATIO {
17994  * SQ_TEX_BORDER_COLOR enum
17997 typedef enum SQ_TEX_BORDER_COLOR {
18005  * SQ_TEX_CLAMP enum
18008 typedef enum SQ_TEX_CLAMP {
18020  * SQ_TEX_DEPTH_COMPARE enum
18023 typedef enum SQ_TEX_DEPTH_COMPARE {
18035  * SQ_TEX_MIP_FILTER enum
18038 typedef enum SQ_TEX_MIP_FILTER {
18046  * SQ_TEX_XY_FILTER enum
18049 typedef enum SQ_TEX_XY_FILTER {
18057  * SQ_TEX_Z_FILTER enum
18060 typedef enum SQ_TEX_Z_FILTER {
18067  * SQ_WATCH_MODES enum
18070 typedef enum SQ_WATCH_MODES {
18078  * SQ_WAVE_FWD_PROG_INTERVAL enum
18081 typedef enum SQ_WAVE_FWD_PROG_INTERVAL {
18089  * SQ_WAVE_SCHED_MODES enum
18092 typedef enum SQ_WAVE_SCHED_MODES {
18099  * SQ_WAVE_TYPE enum
18102 typedef enum SQ_WAVE_TYPE {
18310  * GL1A_PERF_SEL enum
18313 typedef enum GL1A_PERF_SEL {
18341  * GL1C_PERF_SEL enum
18344 typedef enum GL1C_PERF_SEL {
18417  * GL1XA_PERF_SEL enum
18420 typedef enum GL1XA_PERF_SEL {
18448  * GL1XC_PERF_SEL enum
18451 typedef enum GL1XC_PERF_SEL {
18528  * GRBMH_PERF_SEL enum
18531 typedef enum GRBMH_PERF_SEL {
18564  * TA_PERFCOUNT_SEL enum
18567 typedef enum TA_PERFCOUNT_SEL {
18755  * TEX_BC_SWIZZLE enum
18758 typedef enum TEX_BC_SWIZZLE {
18768  * TEX_BORDER_COLOR_TYPE enum
18771 typedef enum TEX_BORDER_COLOR_TYPE {
18779  * TEX_CHROMA_KEY enum
18782 typedef enum TEX_CHROMA_KEY {
18790  * TEX_CLAMP enum
18793 typedef enum TEX_CLAMP {
18805  * TEX_COORD_TYPE enum
18808 typedef enum TEX_COORD_TYPE {
18814  * TEX_DEPTH_COMPARE_FUNCTION enum
18817 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
18829  * TEX_FORMAT_COMP enum
18832 typedef enum TEX_FORMAT_COMP {
18840  * TEX_MAX_ANISO_RATIO enum
18843 typedef enum TEX_MAX_ANISO_RATIO {
18855  * TEX_MIP_FILTER enum
18858 typedef enum TEX_MIP_FILTER {
18866  * TEX_REQUEST_SIZE enum
18869 typedef enum TEX_REQUEST_SIZE {
18877  * TEX_SAMPLER_TYPE enum
18880 typedef enum TEX_SAMPLER_TYPE {
18886  * TEX_XY_FILTER enum
18889 typedef enum TEX_XY_FILTER {
18897  * TEX_Z_FILTER enum
18900 typedef enum TEX_Z_FILTER {
18908  * TVX_TYPE enum
18911 typedef enum TVX_TYPE {
18919  * TA_TC_ADDR_MODES enum
18922 typedef enum TA_TC_ADDR_MODES {
18933  * TA_TC_REQ_MODES enum
18936 typedef enum TA_TC_REQ_MODES {
18948  * TCP_CACHE_POLICIES enum
18951 typedef enum TCP_CACHE_POLICIES {
18959  * TCP_CACHE_STORE_POLICIES enum
18962 typedef enum TCP_CACHE_STORE_POLICIES {
18968  * TCP_COMPRESSION_BYPASS enum
18971 typedef enum TCP_COMPRESSION_BYPASS {
18977  * TCP_COMPRESSION_OVERRIDE enum
18980 typedef enum TCP_COMPRESSION_OVERRIDE {
18986  * TCP_OPCODE_TYPE enum
18989 typedef enum TCP_OPCODE_TYPE {
19001  * TCP_PERFCOUNT_SELECT enum
19004 typedef enum TCP_PERFCOUNT_SELECT {
19084  * TCP_WATCH_MODES enum
19087 typedef enum TCP_WATCH_MODES {
19095  * TCP_WRITE_COMPRESSION_DISABLE enum
19098 typedef enum TCP_WRITE_COMPRESSION_DISABLE {
19108  * TD_PERFCOUNT_SEL enum
19111 typedef enum TD_PERFCOUNT_SEL {
19271  * GL2A_PERF_SEL enum
19274 typedef enum GL2A_PERF_SEL {
19377  * GL2C_PERF_SEL enum
19380 typedef enum GL2C_PERF_SEL {
19550  * SX_BLEND_OPT enum
19553 typedef enum SX_BLEND_OPT {
19565  * SX_DOWNCONVERT_FORMAT enum
19568 typedef enum SX_DOWNCONVERT_FORMAT {
19586  * SX_OPT_COMB_FCN enum
19589 typedef enum SX_OPT_COMB_FCN {
19601  * SX_PERFCOUNTER_VALS enum
19604 typedef enum SX_PERFCOUNTER_VALS {
19690  * CompareFrag enum
19693 typedef enum CompareFrag {
19705  * ConservativeZExport enum
19708 typedef enum ConservativeZExport {
19716  * DbMemArbWatermarks enum
19719 typedef enum DbMemArbWatermarks {
19731  * DbPRTFaultBehavior enum
19734 typedef enum DbPRTFaultBehavior {
19742  * DbPSLControl enum
19745 typedef enum DbPSLControl {
19753  * ForceControl enum
19756 typedef enum ForceControl {
19764  * GLCompressionMode enum
19767 typedef enum GLCompressionMode {
19775  * OreoMode enum
19778 typedef enum OreoMode {
19786  * PerfCounter_Vals enum
19789 typedef enum PerfCounter_Vals {
20177  * PixelPipeCounterId enum
20180 typedef enum PixelPipeCounterId {
20192  * PixelPipeStride enum
20195 typedef enum PixelPipeStride {
20203  * RingCounterControl enum
20206 typedef enum RingCounterControl {
20213  * StencilOp enum
20216 typedef enum StencilOp {
20236  * ZLimitSumm enum
20239 typedef enum ZLimitSumm {
20247  * ZModeForce enum
20250 typedef enum ZModeForce {
20258  * ZOrder enum
20261 typedef enum ZOrder {
20269  * ZSamplePosition enum
20272 typedef enum ZSamplePosition {
20278  * SU_PERFCNT_SEL enum
20281 typedef enum SU_PERFCNT_SEL {
20533  * RMIPerfSel enum
20536 typedef enum RMIPerfSel {
20679  * UTCL1PerfSel enum
20682 typedef enum UTCL1PerfSel {
20756  * GC_EA_SE_PERFCOUNT_SEL enum
20759 typedef enum GC_EA_SE_PERFCOUNT_SEL {
20861  * LSDMA_PERF_SEL enum
20864 typedef enum LSDMA_PERF_SEL {
20993  * EFC_SURFACE_PIXEL_FORMAT enum
20996 typedef enum EFC_SURFACE_PIXEL_FORMAT {