Lines Matching +full:0 +full:x0020000
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
58 ATOM_CRTC1 =0,
64 ATOM_CRTC_INVALID =0xff,
78 ATOM_PPLL_INVALID =0xff,
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
107 ENCODER_REFCLK_SRC_P1PLL =0,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
121 ATOM_DISABLE = 0,
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60,
183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61,
184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
185 ATOM_DGPU_VRAM_TYPE_HBM3 = 0x80,
189 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
190 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
191 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
192 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
193 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
194 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
195 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
196 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
197 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
198 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
216 OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048,
217 OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002,
218 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94,
219 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/
220 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f,
221 OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e,
222 OFFSET_TO_VBIOS_PART_NUMBER = 0x80,
223 OFFSET_TO_VBIOS_DATE = 0x50,
366 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
457 ATOM_HSYNC_POLARITY = 0x0002,
458 ATOM_VSYNC_POLARITY = 0x0004,
459 ATOM_H_REPLICATIONBY2 = 0x0010,
460 ATOM_V_REPLICATIONBY2 = 0x0020,
461 ATOM_INTERLACE = 0x0080,
462 ATOM_COMPOSITESYNC = 0x0040,
492 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
502 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
503 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
504 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
505 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080,
506 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
507 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200,
508 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400,
509 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000,
510 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000,
514 AIR_COOLING = 0x00,
515 LIQUID_COOLING = 0x01
531 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
559 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
570 …uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table ins…
587 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
598 …uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table ins…
622 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
623 …uint8_t hw_blt_mode; //0:HW_BLT_DMA_PIO_MODE; 1:HW_BLT_LITE_SDMA_MODE; 2:HW_B…
633 // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
682 ATOM_PANEL_MISC_FPDI =0x0002,
688 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
689 …eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without A…
690 …eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
711 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
712 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
713 …I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C …
726 …/* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; …
757 * set SRIOV_MSG_SHARE_RESERVATION mask start_address_in_kb = 0
820 ATOM_RECORD_END_TYPE = 0xFF,
833 …uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached …
846 …uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of…
859 …ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW enco…
860 …ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is …
861 …ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified an…
862 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
863 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
864 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board.
865 …ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported…
866 …ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is support…
867 …ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported…
868 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
879 …ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-e…
880 …ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this inter…
907 GPIO_PIN_TYPE_INPUT = 0x00,
908 GPIO_PIN_TYPE_OUTPUT = 0x10,
909 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
912 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
913 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
914 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
915 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
922 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
987 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)
993 MINI_TYPE_NORMAL = 0,
998 …ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP sign…
999 …ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compabili…
1000 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
1001 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
1002 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
1003 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
1004 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
1005 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
1006 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
1026 uint16_t reserved1; //only on USBC case, otherwise always = 0
1027 uint16_t reserved2; //reserved and always = 0
1028 uint16_t reserved3; //reserved and always = 0
1032 uint16_t reserved4; //reserved and always = 0
1215 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02,
1217 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04,
1219 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08,
1221 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20,
1222 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
1295 …uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapp…
1296 …uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not inv…
1303 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001,
1304 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002,
1305 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C,
1306 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip
1307 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip
1308 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip
1316 … // a simple Checksum of the sum of whole structure equal to 0x0.
1343 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1350 uint8_t flashlight_id; // 0: Rear, 1: Front
1369 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1378 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1415 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1425 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1661 …char optionName[29]; //max length of string is 28chars + '\0'. Current design is for …
1705 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1711 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1716 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1717 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1718 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1719 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1720 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1726 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1727 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1728 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1734 OtherMemType = 0x01, ///< Assign 01 to Other
1754 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1955 …t; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1957 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1959 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1961 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1976 …t; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1978 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1980 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1982 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1984 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
2009 …t; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
2011 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
2013 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
2015 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
2017 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
2052 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
2482 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
2494 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
2576 uint8_t LedPin0; // GPIO number for LedPin[0]
2747 uint8_t LedPin0; // GPIO number for LedPin[0]
2869 uint8_t LedPin0; // GPIO number for LedPin[0]
3135 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001,
3136 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002,
3137 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004,
3138 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008,
3139 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010,
3140 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020,
3187 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001,
3188 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002,
3189 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004,
3190 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008,
3191 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010,
3192 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000,
3222 …uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 m…
3232 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3233 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3236 char dram_pnstring[20]; // part number end with '0'.
3258 Data Table vram_info v3.0 structure
3309 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
3345 …uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 m…
3355 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3356 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3363 char dram_pnstring[20]; // part number end with '0'
3396 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3397 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3407 char dram_pnstring[40]; // part number end with '0'.
3543 …VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage…
3558 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
3559 …uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in un…
3561 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
3567 VOLTAGE_DATA_ONE_BYTE = 0,
3581 …uint8_t gpio_control_id; // default is 0 which indicate control through CG VI…
3592 …dline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset tri…
3661 b3NORMAL_ENGINE_INIT = 0,
3662 b3SRIOV_SKIP_ASIC_INIT = 0x02,
3663 b3SRIOV_LOAD_UCODE = 0x40,
3668 b3NORMAL_MEM_INIT = 0,
3669 b3DRAM_SELF_REFRESH_EXIT =0x20,
3694 b3NORMAL_CHANGE_CLOCK = 0,
3695 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
3696 …b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store speci…
3752 …uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2…
3757 ATOM_SET_VOLTAGE = 0,
3779 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
3780 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
3781 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
3796 …uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, …
3797 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
3834 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3837 …uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid wh…
3842 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
3849 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
3863 SMU11_SYSPLL0_ID = 0,
3873 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
3882 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
3886 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
3890 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
3894 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
3898 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
3904 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
3910 SMU12_SYSPLL0_ID = 0,
3918 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK
3932 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK
3939 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK
3943 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK
3947 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK
4007 UMC60_UCODE_FUNC_ID_REINIT = 0,
4045 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
4046 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
4047 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
4048 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
4049 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
4050 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
4051 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
4052 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
4053 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
4054 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
4055 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
4061 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disab…
4062 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set…
4063 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set…
4064 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set…
4077 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
4079 …uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when u…
4086 DCE_CLOCK_TYPE_DISPCLK = 0,
4094 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
4095 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
4096 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
4097 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
4098 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
4104 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
4105 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disab…
4106 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set…
4107 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set…
4108 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set…
4109 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
4133 ATOM_BLANKING_OFF = 0,
4206 HW_I2C_READ = 0,
4207 I2C_2BYTE_ADDR = 0x02,
4208 HW_I2C_SMBUS_BYTE_WR = 0x04,
4233 …uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
4257 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
4259 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
4260 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
4261 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
4262 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
4263 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
4264 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
4265 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
4266 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
4267 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
4268 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
4269 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
4270 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
4276 DP_PANEL_MODE_DISABLE = 0x00,
4277 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
4278 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
4284 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
4285 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
4286 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
4287 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
4288 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
4289 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
4290 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
4291 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
4296 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4308 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4320 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4329 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4350 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
4358 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
4374 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
4393 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
4394 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
4395 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
4396 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
4397 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
4398 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
4399 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
4406 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
4407 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
4408 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
4409 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
4410 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
4411 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
4412 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
4418 DP_LANE_SET__0DB_0_4V = 0x00,
4419 DP_LANE_SET__0DB_0_6V = 0x01,
4420 DP_LANE_SET__0DB_0_8V = 0x02,
4421 DP_LANE_SET__0DB_1_2V = 0x03,
4422 DP_LANE_SET__3_5DB_0_4V = 0x08,
4423 DP_LANE_SET__3_5DB_0_6V = 0x09,
4424 DP_LANE_SET__3_5DB_0_8V = 0x0a,
4425 DP_LANE_SET__6DB_0_4V = 0x10,
4426 DP_LANE_SET__6DB_0_6V = 0x11,
4427 DP_LANE_SET__9_5DB_0_4V = 0x18,
4451 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
4452 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
4453 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
4454 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
4455 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
4456 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
4457 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
4458 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
4464 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
4465 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
4466 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
4467 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
4468 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
4469 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
4470 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
4471 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
4472 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
4503 uint8_t tableUUID[16]; //0x24
4504 …uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning …
4505 …uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning o…
4506 uint32_t reserved[4]; //0x3C
4510 uint32_t pcibus; //0x4C
4511 uint32_t pcidevice; //0x50
4512 uint32_t pcifunction; //0x54
4513 uint16_t vendorid; //0x58
4514 uint16_t deviceid; //0x5A
4515 uint16_t ssvid; //0x5C
4516 uint16_t ssid; //0x5E
4517 uint32_t revision; //0x60
4518 uint32_t imagelength; //0x64
4543 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
4555 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
4556 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
4557 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
4558 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
4559 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
4560 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
4561 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
4562 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
4563 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
4567 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
4569 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
4570 ATOM_DEVICE_DPMS_STATE =0x00010000,
4575 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
4576 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
4577 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
4578 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
4579 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
4580 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
4581 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
4582 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
4586 ATOM_DISPLAY_LCD1_REQ =0x0002,
4587 ATOM_DISPLAY_DFP1_REQ =0x0008,
4588 ATOM_DISPLAY_DFP2_REQ =0x0080,
4589 ATOM_DISPLAY_DFP3_REQ =0x0200,
4590 ATOM_DISPLAY_DFP4_REQ =0x0400,
4591 ATOM_DISPLAY_DFP5_REQ =0x0800,
4592 ATOM_DISPLAY_DFP6_REQ =0x0040,
4593 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
4602 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
4603 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
4607 ATOM_PRE_OS_MODE_MASK =0x00000003,
4608 ATOM_PRE_OS_MODE_VGA =0x00000000,
4609 ATOM_PRE_OS_MODE_VESA =0x00000001,
4610 ATOM_PRE_OS_MODE_GOP =0x00000002,
4611 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
4612 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
4613 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
4614 ATOM_ASIC_INIT_COMPLETE =0x00000200,
4616 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,