Lines Matching +full:sw +full:- +full:mode
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
109 #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
235 …USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change t…
236 …USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the …
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
258 …USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change t…
259 …USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the …
273 …USHORT ASIC_Init; //Function Table, used by various SW components,lat…
275 …USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW comp…
278 …USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW comp…
279 …USHORT EnableCRTCMemReq; //Function Table,directly used by various SW compon…
280 …USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW comp…
281 …USHORT DVOEncoderControl; //Function Table,directly used by various SW compon…
283 …USHORT SetEngineClock; //Function Table,directly used by various SW compon…
284 …USHORT SetMemoryClock; //Function Table,directly used by various SW compon…
285 …USHORT SetPixelClock; //Function Table,directly used by various SW compon…
286 …USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW comp…
287 …USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW comp…
288 …USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW comp…
290 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
291 …USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW comp…
294 …USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW compon…
295 …USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW componen…
296 …USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW compon…
297 …USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW compon…
298 …USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW compon…
299 …USHORT DVOOutputControl; //Atomic Table, directly used by various SW compon…
302 …USHORT SMC_Init; //Function Table,directly used by various SW compon…
307 …USHORT BlankCRTC; //Atomic Table, directly used by various SW compon…
308 …USHORT EnableCRTC; //Atomic Table, directly used by various SW compon…
309 …USHORT GetPixelClock; //Atomic Table, directly used by various SW compon…
310 …USHORT EnableVGA_Render; //Function Table,directly used by various SW compon…
312 …USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW compon…
313 …USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,late…
315 …USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW compon…
320 …USHORT GetMemoryClock; //Atomic Table, directly used by various SW compon…
321 …USHORT GetEngineClock; //Atomic Table, directly used by various SW compon…
322 …USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW compon…
323 …USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW compon…
324 …USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW compon…
328 …USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW comp…
329 …USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW comp…
330 …USHORT SpeedFanControl; //Function Table,indirectly used by various SW comp…
331 …USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW compon…
332 …USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW comp…
333 …USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW comp…
334 …USHORT Gfx_Init; //Atomic Table, indirectly used by various SW comp…
336 …USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW comp…
338 …USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW compon…
339 …USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW compon…
340 … //Function Table,directly and/or indirectly used by various SW components,latest ve…
341 …USHORT DAC1OutputControl; //Atomic Table, directly used by various SW compon…
342 …USHORT ReadEfuseValue; //Atomic Table, directly used by various SW compon…
344 …USHORT ClockSource; //Atomic Table, indirectly used by various SW comp…
345 …USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW comp…
346 …USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW comp…
347 …USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW componen…
348 …USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW componen…
349 …USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW componen…
350 …USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW componen…
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …R ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
598 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
606 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
611 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
866 …NFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
958 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1004 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
1011 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1063 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
1064 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
1101 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1160 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1165 // [1]=0: InCoherent mode
1166 // =1: Coherent Mode
1240 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1244 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1288 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1305 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1309 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1327 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1380 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1384 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1401 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1405 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1422 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1479 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI…
1482 UCHAR ucLaneNum; // indicate lane number 1-8
1484 UCHAR ucDigMode; // indicate DIG mode
1566 …UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP…
1571 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1618 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1778 …UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1807 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1901 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1924 UCHAR ucEncoderMode; // Encoder mode:
1929 // =0: XTLAIN( default mode )
1930 // =1: other external clock source, which is pre-defined
1972 UCHAR ucEncoderMode; // Encoder mode:
1977 // =0: XTLAIN( default mode )
1978 // =1: other external clock source, which is pre-defined
2022 UCHAR ucEncoderMode; // Encoder mode:
2026 // =0: XTLAIN( default mode )
2046 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: D…
2047 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO:…
2048 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO:…
2049 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO:…
2097 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE:…
2098 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATI…
2099 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATI…
2100 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATI…
2134 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
2156 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
2157 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
2203 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
2311 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2312 // Bit[1]: 1-Ext. 0-Int.
2336 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2337 // Bit[1]: 1-Ext. 0-Int.
2532 // bit1=0: non-coherent mode
2533 // =1: coherent mode
2607 …AR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2789 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2791 …USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was…
2793 USHORT SMU_Info; // Shared by various SW components,latest version 1.1
2795 …USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will…
2796 …USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will…
2797 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2799 …USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will…
2800 …USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new …
2803 …USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, use…
2804 …USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2806 …USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, onl…
2807 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2815 USHORT IntegratedSystemInfo; // Shared by various SW components
2816 …_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2817 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2818 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
3009 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3046 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3084 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3123 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3127 … usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock …
3175 … usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock …
3217 //Bit[4]==1: P/2 mode, ==0: P/1 mode
3234 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
3235 … IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
3237 …MemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
3265 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data…
3266 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW c…
3268 SW components can access the IGP system infor structure in the same way as before
3310 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
3315 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3316 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3317 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
3320 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
3321 … at AMD overdrived state or user customized mode. In this case, driver will just stick to this bo…
3332 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using l…
3333 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
3339 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
3341 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3342 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
3345 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
3346 …[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station…
3349 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
3351 [15:8] - Lane configuration attribute;
3352 [23:16]- Connector type, possible value:
3358 [31:24]- Reserved
3366 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
3374 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
3375 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
3376 …GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_US…
3377 …PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE…
3378 …GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYST…
3380 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3409 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3630 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3631 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3632 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3633 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3634 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3635 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3636 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3637 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3638 // Bit 8 = 0 - no CV support= 1- CV is supported
3639 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3640 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3641 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3649 // [7:0] - I2C LINE Associate ID
3650 // = 0 - no I2C
3651 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3652 // = 0, [6:0]=SW assisted I2C ID
3653 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3655 // = 3-7 Reserved for future I2C engines
3656 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3761 // usModeMiscInfo-
3773 //usRefreshRate-
3949 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3958 // 0 0 0 - Color bit depth is undefined
3959 // 0 0 1 - 6 Bits per Primary Color
3960 // 0 1 0 - 8 Bits per Primary Color
3961 // 0 1 1 - 10 Bits per Primary Color
3962 // 1 0 0 - 12 Bits per Primary Color
3963 // 1 0 1 - 14 Bits per Primary Color
3964 // 1 1 0 - 16 Bits per Primary Color
3965 // 1 1 1 - Reserved
4014 // Bit7-3: Reserved
4033 …ORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
4052 // 0 0 0 - Color bit depth is undefined
4053 // 0 0 1 - 6 Bits per Primary Color
4054 // 0 1 0 - 8 Bits per Primary Color
4055 // 0 1 1 - 10 Bits per Primary Color
4056 // 1 0 0 - 12 Bits per Primary Color
4057 // 1 0 1 - 14 Bits per Primary Color
4058 // 1 1 0 - 16 Bits per Primary Color
4059 // 1 1 1 - Reserved
4069 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
4076 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
4077 …_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW in…
4078 #define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init
4219 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down …
4222 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
4236 … (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
4294 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
4318 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
4322 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
4324 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
4368 //ucGPIO_ID pre-define id for multiple usage
4380 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; u…
4382 // Thermal interrupt output->system thermal chip GPIO pin
4437 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
4438 …//bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
4439 …//bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
4459 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4476 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4650 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recov…
4788 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4844 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4850 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4864 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
4874 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
4957 …// override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = ma…
5019 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - Ba…
5112 …UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leaka…
5117 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
5118 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
5119 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
5120 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
5122 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5123 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5124 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5142 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
5147 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5158 …ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PH…
5159 …CHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
5169 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12
5180 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2
5181 // 14:7 - PSI0_VID
5182 // 6 - PSI0_EN
5183 // 5 - PSI1
5184 // 4:2 - load line slope trim.
5185 // 1:0 - offset trim,
5197 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
5214 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2
5272 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5276 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5278 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5282 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5286 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5288 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5523 …ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="…
5524 …ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." u…
5525 … //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode…
5526 …A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)."…
5527 …ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." un…
5528 …ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="1…
5529 …6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)."…
5530 …; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." …
5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5809 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5825 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
5826 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
5827 bit[3]=0: Enable HW AUX mode detection logic
5828 =1: Disable HW AUX mode dettion logic
5831 …MFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5834 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5835 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5837 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5840 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5843 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5854 Bit[1]=0: DDR-DLL shut-down feature disabled.
5855 1: DDR-DLL shut-down feature enabled.
5856 Bit[2]=0: DDR-PLL Power down feature disabled.
5857 1: DDR-PLL Power down feature enabled.
5876 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5877 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5889 … [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel …
5891 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6029 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6050 …S fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is con…
6051 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
6052 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
6053 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
6054 =1: DP mode use single PLL mode
6055 bit[3]=0: Enable AUX HW mode detection logic
6056 =1: Disable AUX HW mode detection logic
6060 …MFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
6063 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6064 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6066 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6069 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6072 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6083 Bit[1]=0: DDR-DLL shut-down feature disabled.
6084 1: DDR-DLL shut-down feature enabled.
6085 Bit[2]=0: DDR-PLL Power down feature disabled.
6086 1: DDR-PLL Power down feature enabled.
6107 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
6108 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6120 … [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel …
6122 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6129 … default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6132 …efault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6136 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6140 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6231 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6254 …S fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is con…
6257 bit[3]=0: Enable AUX HW mode detection logic
6258 =1: Disable AUX HW mode detection logic
6262 …MFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
6265 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6266 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6268 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6271 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6274 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6284 Bit[1]=0: DDR-DLL shut-down feature disabled.
6285 1: DDR-DLL shut-down feature enabled.
6286 Bit[2]=0: DDR-PLL Power down feature disabled.
6287 1: DDR-PLL Power down feature enabled.
6308 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
6326 … [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel …
6328 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6336 … default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6340 …efault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6344 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6348 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6367 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
6368 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
6369 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
6370 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
6598 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
6601 …s; //Indicates how many bytes SW needs to write to th…
6606 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C pro…
6609 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
6639 //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a cloc…
6845 …S_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
7146 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
7148 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
7149 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
7153 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
7154 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
7390 UCHAR ucVMode_Num; //Video mode number
7391 UCHAR ucTV_Mode_Num; //Internal TV mode number
7577 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
7615 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7616 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7633 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
7642 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7643 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7653 USHORT usMRS; // mode register
7657 USHORT usEMRS; // extended mode register
7688 USHORT usMRS; // mode register
7689 USHORT usEMRS; // extended mode register
7724 USHORT usMRS; // mode register
7725 USHORT usEMRS; // extended mode register
7769 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
7776 … ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
7794 … ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7815 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7817 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7820 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7825 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7857 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7859 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7862 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7867 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7876 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7889 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7891 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7894 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7899 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7908 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7924 …UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memo…
7927 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7929 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7938 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7968 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
8104 /****************************SW I2C CNTL DEFINITIONS**********************/
8193 USHORT ModeAttributes; // dw ? ; mode attributes
8200 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
8225 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
8229 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8230 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
8244 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
8573 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8574 …gListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's …
8575 …ttingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting fo…
8582 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8583 …gListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's …
8584 …ttingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting fo…
8594 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8595 …gListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's …
8596 …ttingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting fo…
8601 … // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis…
8602 … // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis…
8603 … // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis…
8604 … // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis…
8605 … // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis…
8606 …TING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Lin…
8773 // [7:4] - connector type
8774 // = 1 - VGA connector
8775 // = 2 - DVI-I
8776 // = 3 - DVI-D
8777 // = 4 - DVI-A
8778 // = 5 - SVIDEO
8779 // = 6 - COMPOSITE
8780 // = 7 - LVDS
8781 // = 8 - DIGITAL LINK
8782 // = 9 - SCART
8783 // = 0xA - HDMI_type A
8784 // = 0xB - HDMI_type B
8785 // = 0xE - Special case1 (DVI+DIN)
8787 // [3:0] - DAC Associated
8788 // = 0 - no DAC
8789 // = 1 - DACA
8790 // = 2 - DACB
8791 // = 3 - External DAC
8856 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8950 …is bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
8966 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
8974 …SCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
8976 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
8986 …IDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will…
8987 …//If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video pla…
9095 // Following definitions are for compatiblity issue in different SW components.
9223 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )