Lines Matching +full:bit0 +full:- +full:7
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
119 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
120 #define ATOM_INIT (ATOM_DISABLE+7)
136 #define ATOM_TV_PAL60 7
156 // Bit0:{=0:single, =1:dual},
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
393 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
394 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
396 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
397 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
427 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
428 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
432 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
433 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
587 UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 )
598 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
606 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
611 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
813 …UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as …
816 // 7: ATOM_ENCODER_INIT Initialize DAC
958 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1011 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1064 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
1101 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1172 // =0: lane 0~3 or 0~7
1173 // =1: lane 4~7
1219 #define ATOM_TRANSMITTER_ACTION_INIT 7
1241 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1243 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1257 //Bit0
1306 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1308 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1336 //Bit0
1379 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1380 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1384 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1385 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1402 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1404 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1435 //Bit0
1482 UCHAR ucLaneNum; // indicate lane number 1-8
1566 …UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP…
1571 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1848 …UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device i…
1901 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1930 // =1: other external clock source, which is pre-defined
1932 // bit[7:5]: reserved.
1978 // =1: other external clock source, which is pre-defined
1980 // bit[7:5]: reserved.
2046 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: D…
2047 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO:…
2048 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO:…
2049 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO:…
2055 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
2097 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE:…
2098 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATI…
2099 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATI…
2100 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATI…
2156 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
2157 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
2203 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
2311 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2312 // Bit[1]: 1-Ext. 0-Int.
2314 // Bits[7:4] reserved
2316 …USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[…
2336 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2337 // Bit[1]: 1-Ext. 0-Int.
2339 // Bits[7:4] reserved
2341 …USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[…
2403 UCHAR ucMisc; // bit0=0: Enable single link
2426 UCHAR ucTruncate; // bit0=0: Disable truncate
2430 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2434 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2474 …UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1…
2532 // bit1=0: non-coherent mode
2626 #define VOLTAGE_TYPE_MVPP 7
2816 …_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2844 …o; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2857 … ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2858 … ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2860 …er voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2861 … input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2862 …AR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2863 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2864 …eoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2865 …eoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2866 …eoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2867 …eoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2868 …eoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
3009 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3046 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3084 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3123 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3141 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID
3178 …PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID,…
3215 …USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI su…
3218 …USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_S…
3224 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[…
3234 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
3252 … duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it…
3286 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3310 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
3315 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3316 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3317 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
3320 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
3321 … or user customized mode. In this case, driver will just stick to this boot-up mode. No other Pow…
3332 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using l…
3339 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
3341 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3342 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
3345 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
3346 …7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station …
3349 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
3351 [15:8] - Lane configuration attribute;
3352 [23:16]- Connector type, possible value:
3358 [31:24]- Reserved
3366 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
3370 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits rese…
3380 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3409 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3470 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3630 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3631 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3632 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3633 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3634 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3635 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3636 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3637 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3638 // Bit 8 = 0 - no CV support= 1- CV is supported
3639 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3640 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3641 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3649 // [7:0] - I2C LINE Associate ID
3650 // = 0 - no I2C
3651 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3653 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3655 // = 3-7 Reserved for future I2C engines
3656 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3761 // usModeMiscInfo-
3773 //usRefreshRate-
3907 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3927 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3958 // 0 0 0 - Color bit depth is undefined
3959 // 0 0 1 - 6 Bits per Primary Color
3960 // 0 1 0 - 8 Bits per Primary Color
3961 // 0 1 1 - 10 Bits per Primary Color
3962 // 1 0 0 - 12 Bits per Primary Color
3963 // 1 0 1 - 14 Bits per Primary Color
3964 // 1 1 0 - 16 Bits per Primary Color
3965 // 1 1 1 - Reserved
4000 // Bit0: {=0:single, =1:dual},
4011 … // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
4014 // Bit7-3: Reserved
4052 // 0 0 0 - Color bit depth is undefined
4053 // 0 0 1 - 6 Bits per Primary Color
4054 // 0 1 0 - 8 Bits per Primary Color
4055 // 0 1 1 - 10 Bits per Primary Color
4056 // 1 0 0 - 12 Bits per Primary Color
4057 // 1 0 1 - 14 Bits per Primary Color
4058 // 1 1 0 - 16 Bits per Primary Color
4059 // 1 1 1 - Reserved
4076 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
4077 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip with…
4179 //ATOM_TV_PAL60 7
4209 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
4210 …UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change acc…
4222 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
4236 … (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
4294 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
4318 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
4322 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
4324 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
4368 //ucGPIO_ID pre-define id for multiple usage
4380 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; u…
4382 // Thermal interrupt output->system thermal chip GPIO pin
4401 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
4414 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
4435 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
4450 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
4459 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4476 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4569 #define EXT_HPDPIN_LUTINDEX_7 7
4579 #define EXT_AUXDDC_LUTINDEX_7 7
4587 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: fro…
4607 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: …
4642 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
4650 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recov…
4659 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
4682 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
4788 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4819 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
4844 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4846 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4848 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4850 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4864 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
4868 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4870 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4874 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
5018 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
5019 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - Ba…
5117 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
5118 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
5119 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
5120 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
5122 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5123 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5124 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5147 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5181 // 14:7 - PSI0_VID
5182 // 6 - PSI0_EN
5183 // 5 - PSI1
5184 // 4:2 - load line slope trim.
5185 // 1:0 - offset trim,
5208 UCHAR ucDPMState; // DPMState0~7
5272 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5276 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5278 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5282 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5286 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5288 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5402 …USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m ma…
5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5809 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5834 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5835 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5837 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5840 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5843 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5854 Bit[1]=0: DDR-DLL shut-down feature disabled.
5855 1: DDR-DLL shut-down feature enabled.
5856 Bit[2]=0: DDR-PLL Power down feature disabled.
5857 1: DDR-PLL Power down feature enabled.
5869 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5876 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5877 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5889 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
6029 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6063 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6064 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6066 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6069 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6072 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6083 Bit[1]=0: DDR-DLL shut-down feature disabled.
6084 1: DDR-DLL shut-down feature enabled.
6085 Bit[2]=0: DDR-PLL Power down feature disabled.
6086 1: DDR-PLL Power down feature enabled.
6100 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
6107 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
6108 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6120 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
6129 … default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6132 …efault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6136 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6140 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6231 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6265 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6266 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6268 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6271 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6274 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6284 Bit[1]=0: DDR-DLL shut-down feature disabled.
6285 1: DDR-DLL shut-down feature enabled.
6286 Bit[2]=0: DDR-PLL Power down feature disabled.
6287 1: DDR-PLL Power down feature enabled.
6300 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
6308 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
6326 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
6336 … default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6340 …efault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6344 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6348 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6367 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
6368 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
6369 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
6370 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
6530 ULONG ulReserved[7];
6647 #define ASIC_INTERNAL_SS_ON_DP 7
6661 …UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Sp…
6692 …UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Sp…
6716 #define ATOM_DOS_MODE_INFO_DEF 7
7052 #define ATOM_S6_DOCK_STATE_SHIFT 7
7146 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
7148 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
7149 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
7153 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
7154 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
7577 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
7606 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
7608 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
7614 … ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, …
7615 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7616 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7633 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
7635 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
7641 … ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, …
7642 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7643 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7677 … ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infi…
7704 … ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infi…
7740 … ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infi…
7769 …CHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:…
7779 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7794 … ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7815 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
7817 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7820 …Misc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstl…
7823 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7825 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7857 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
7859 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7862 …Misc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstl…
7865 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7867 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7876 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7889 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
7891 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7894 …Misc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstl…
7897 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7899 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7908 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7924 …UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memo…
7927 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7928 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7929 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7935 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7938 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7965 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7968 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
8006 …ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) …
8128 #define VESA_MODE_WIN_ATTRIBUTE 7
8216 //; Direct Color fields(required for direct/6 and YUV/7 memory models)
8229 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8230 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
8273 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
8567 #define SELECT_CRTC_PIXEL_RATE 7
8573 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8574 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8575 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8582 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8583 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8584 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8594 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8595 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8596 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8601 …fset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Lin…
8602 …t of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8603 … of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8604 …set of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Lin…
8605 …f PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8606 …TING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Lin…
8755 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8760 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8765 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8773 // [7:4] - connector type
8774 // = 1 - VGA connector
8775 // = 2 - DVI-I
8776 // = 3 - DVI-D
8777 // = 4 - DVI-A
8778 // = 5 - SVIDEO
8779 // = 6 - COMPOSITE
8780 // = 7 - LVDS
8781 // = 8 - DIGITAL LINK
8782 // = 9 - SCART
8783 // = 0xA - HDMI_type A
8784 // = 0xB - HDMI_type B
8785 // = 0xE - Special case1 (DVI+DIN)
8787 // [3:0] - DAC Associated
8788 // = 0 - no DAC
8789 // = 1 - DACA
8790 // = 2 - DACB
8791 // = 3 - External DAC
8856 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8922 …UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,…
8966 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
8976 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
8986 …O2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver …
9223 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )