Lines Matching +full:8 +full:khz
85 #define ATOM_EXT_PLL1 8
86 #define ATOM_GCK_DFS 8
121 #define ATOM_GET_STATUS (ATOM_DISABLE+8)
137 #define ATOM_TV_SECAM 8
393 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
394 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
396 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
397 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
478 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
479 ULONG ulClockFreq:24; // in unit of 10kHz
481 ULONG ulClockFreq:24; // in unit of 10kHz
482 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
510 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
517 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
521 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
586 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
687 ULONG ulTargetEngineClock; //In 10Khz unit
692 ULONG ulTargetEngineClock; //In 10Khz unit
698 ULONG ulTargetEngineClock; //In 10Khz unit
708 ULONG ulTargetMemoryClock; //In 10Khz unit
713 ULONG ulTargetMemoryClock; //In 10Khz unit
722 ULONG ulDefaultEngineClock; //In 10Khz unit
723 ULONG ulDefaultMemoryClock; //In 10Khz unit
735 ULONG ucClkFlag:8;
740 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit
741 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit
747 ULONG ulReserved[8];
812 USHORT usPixelClock; // in 10KHz; for bios convenient
828 USHORT usPixelClock; // in 10KHz; for bios convenient
906 USHORT usPixelClock; // in 10KHz; for bios convenient
987 USHORT usPixelClock; // in 10KHz; for bios convenient
1043 USHORT usPixelClock; // in 10KHz; for bios convenient
1087 ULONG ulPixelClock; // Pixel Clock in 10Khz
1099 ULONG ulSymClock; // Symbol Clock in 10Khz
1158 USHORT usPixelClock; // in 10KHz; for bios convenient
1159 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1164 // =1: 8 lane Link ( Dual Links TMDS )
1174 // =2: lane 8~11 or 8~15
1220 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
1286 USHORT usPixelClock; // in 10KHz; for bios convenient
1287 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1325 USHORT usPixelClock; // in 10KHz; for bios convenient
1326 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1420 USHORT usPixelClock; // in 10KHz; for bios convenient
1421 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1479 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI…
1482 UCHAR ucLaneNum; // indicate lane number 1-8
1569 ULONG ulSymClock; // Symbol Clock in 10Khz
1613 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1808 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR
1819 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1839 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1886 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1948 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1955 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
2054 …ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequ…
2076 …ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, retur…
2186 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
2195 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2202 //Maxium 8 bytes,the data read in will be placed in the parameter space.
2316 …RT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
2330 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
2341 …RT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
2357 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
2376 ULONG ulTargetMemoryClock; //In 10Khz unit
2402 USHORT usPixelClock; // in 10KHz; for bios convenient
2422 USHORT usPixelClock; // in 10KHz; for bios convenient
2627 #define VOLTAGE_TYPE_LEDDPM 8
2649 #define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7…
2752 ULONG ucDfsDivider:8;
2765 USHORT usPixelClock; // in 10KHz; for bios convenient
2952 ULONG ulDefaultEngineClock; //In 10Khz unit
2953 ULONG ulDefaultMemoryClock; //In 10Khz unit
2954 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2955 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2956 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2957 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2958 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2959 ULONG ulASICMaxEngineClock; //In 10Khz unit
2960 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2964 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2965 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2966 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2967 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2968 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2969 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2970 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2971 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2972 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2973 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above…
2975 USHORT usReferenceClock; //In 10Khz unit
2986 ULONG ulDefaultEngineClock; //In 10Khz unit
2987 ULONG ulDefaultMemoryClock; //In 10Khz unit
2988 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2989 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2990 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2991 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2992 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2993 ULONG ulASICMaxEngineClock; //In 10Khz unit
2994 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2999 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3000 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3001 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3002 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3003 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3004 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3005 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3006 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3007 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3008 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3009 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3011 USHORT usReferenceClock; //In 10Khz unit
3022 ULONG ulDefaultEngineClock; //In 10Khz unit
3023 ULONG ulDefaultMemoryClock; //In 10Khz unit
3024 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3025 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3026 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3027 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3028 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3029 ULONG ulASICMaxEngineClock; //In 10Khz unit
3030 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3035 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3036 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3037 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3038 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3039 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3040 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3041 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3042 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3043 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3044 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3045 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3046 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3048 USHORT usReferenceClock; //In 10Khz unit
3059 ULONG ulDefaultEngineClock; //In 10Khz unit
3060 ULONG ulDefaultMemoryClock; //In 10Khz unit
3061 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3062 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3063 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3064 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3065 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3066 ULONG ulASICMaxEngineClock; //In 10Khz unit
3067 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3073 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3074 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3075 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3076 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3077 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3078 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3079 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3080 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3081 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3082 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3083 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3084 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3086 USHORT usReferenceClock; //In 10Khz unit
3098 ULONG ulDefaultEngineClock; //In 10Khz unit
3099 ULONG ulDefaultMemoryClock; //In 10Khz unit
3102 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3103 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3104 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3106 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
3113 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3114 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3115 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3116 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3117 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3118 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3119 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3120 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3121 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3122 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3123 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3125 USHORT usCoreReferenceClock; //In 10Khz unit
3126 USHORT usMemoryReferenceClock; //In 10Khz unit
3127 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
3148 ULONG ulDefaultEngineClock; //In 10Khz unit
3149 ULONG ulDefaultMemoryClock; //In 10Khz unit
3150 ULONG ulSPLL_OutputFreq; //In 10Khz unit
3151 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
3152 … ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
3153 … ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
3154 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3156 …ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency…
3163 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3168 …USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz uni…
3169 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3170 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3173 USHORT usCoreReferenceClock; //In 10Khz unit
3174 USHORT usMemoryReferenceClock; //In 10Khz unit
3175 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
3203 ULONG ulBootUpEngineClock; //in 10kHz unit
3204 ULONG ulBootUpMemoryClock; //in 10kHz unit
3205 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
3206 ULONG ulMinSystemMemoryClock; //in 10kHz unit
3218 …USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_S…
3227 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
3248 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max …
3249 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min …
3251 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
3252 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the valu…
3254 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the ma…
3255 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min…
3275 ULONG ulBootUpEngineClock; //in 10kHz unit
3277 ULONG ulBootUpUMAClock; //in 10kHz unit
3278 ULONG ulBootUpSidePortClock; //in 10kHz unit
3279 ULONG ulMinSidePortClock; //in 10kHz unit
3296 ULONG ulHTLinkFreq; //in 10Khz
3303 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
3304 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
3315 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3316 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3317 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
3334 Bit[8]=1: CDLF is supported and enabled on current system.
3341 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3345 …ot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
3346 …ctor on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
3349 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
3351 [15:8] - Lane configuration attribute;
3383 ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
3449 ULONG ulBootUpEngineClock; //in 10kHz unit
3450 …ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the sourc…
3451 …ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relation…
3452 ULONG ulBootUpUMAClock; //in 10kHz unit
3453 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3638 // Bit 8 = 0 - no CV support= 1- CV is supported
3855 USHORT usPixelClock; //in 10Khz unit
3960 // 0 1 0 - 8 Bits per Primary Color
4054 // 0 1 0 - 8 Bits per Primary Color
4180 //ATOM_TV_SECAM 8
4234 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8=…
4636 …UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert…
4683 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD…
4820 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8
5044 …UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with…
5121 #define VOLTAGE_OBJ_EVV 8
5215 ATOM_EVV_DPM_INFO asEvvDpmList[8];
5240 …USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xf…
5276 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5286 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5504 ULONG ulReserved[8]; // Reserved for future ASIC
5593 ULONG ulaTDClimitPerDPM[8];
5594 ULONG ulaNoCalcVddcPerDPM[8];
5642 ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8];
5713 …mSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5720 …mSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5725 …upportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5809 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
5810 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5811 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5851 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
5876 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5877 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6029 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
6030 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6031 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6080 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
6107 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
6108 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6129 …=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->…
6136 …=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following:…
6159 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB ps…
6231 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
6232 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6233 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6308 …eed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
6336 …=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->…
6344 …=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following:…
6367 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
6411 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8];
6486 UCHAR strModuleName[8];
6493 UCHAR strName[8];
6511 ULONG ulReserved0[8];
6531 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8];
6631 … ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
6633 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
6648 #define ASIC_INTERNAL_SS_ON_DCPLL 8
6656 …rgetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6687 …rgetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6717 #define ATOM_I2C_CHANNEL_STATUS_DEF 8
6823 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
6929 #define ATOM_S4_LCD1_REFRESH_SHIFT 8
6971 (ATOM_S5_DOS_FORCE_CVb3<<8))
7053 #define ATOM_S6_CRITICAL_STATE_SHIFT 8
7078 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
7104 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SH…
7105 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHAN…
7106 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTN…
7107 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHAN…
7108 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_…
7110 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_S…
7111 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_S…
7113 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING…
7114 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_…
7115 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_…
7117 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STA…
7118 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWE…
7119 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_S…
7121 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_ST…
7122 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_ST…
7124 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_…
7125 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_…
7127 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_…
7128 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_…
7130 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_C…
7132 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STA…
7134 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISP…
7135 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_…
7136 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_…
7137 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_…
7171 ULONG ulTargetMemoryClock; //In 10Khz unit
7273 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address
7274 USHORT usMemorySize; //8Kb blocks aligned
7451 ULONG ucMemBlkId:8;
7455 ULONG ucMemBlkId:8;
7608 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
7635 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
7651 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory…
7687 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memor…
7723 …ULONG ulClkRange; // memory clock in 10kHz unit, when …
7775 …UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
7820 … // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7838 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64…
7862 … // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7874 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64…
7894 … // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7906 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64…
7936 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7955 … // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bi…
7966 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7990 …UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+…
8061 …UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+…
8481 …ne DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
8568 #define SELECT_VGA_BLK 8
8737 USHORT usMaxFrequency; // in 10kHz unit
8781 // = 8 - DIGITAL LINK
8868 USHORT usMaxFrequency; // in 10Khz
9040 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
9253 UCHAR OemTableId[8]; //UINT64 OemTableId;