Lines Matching +full:ip +full:- +full:block

55 * DOC: IP Blocks
57 * GPUs are composed of IP (intellectual property) blocks. These
58 * IP blocks provide various functionalities: display, graphics,
59 * video decode, etc. The IP blocks that comprise a particular GPU
61 * acquires the list of IP blocks for the GPU in use on initialization.
66 * IP block implementations are named using the following convention:
71 * enum amd_ip_block_type - Used to classify IP blocks by functionality.
83 * @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
85 * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
90 * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types
183  * enum PP_FEATURE_MASK - Used to mask power play features.
199  * @PP_OVERDRIVE_MASK: Over- and under-clocking support.
255  * enum DC_DEBUG_MASK - Bits that are useful for debugging the Display Core IP
259 	 * @DC_DISABLE_PIPE_SPLIT: If set, disable pipe-splitting
279 	 * @DC_DISABLE_PSR: If set, disable Panel self refresh v1 and PSR-SU
290 	 * @DC_DISABLE_MPO: If set, disable multi-plane offloading
345  * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
346  * @name: Name of IP block
348  *              does not configure hw - Optional
349  * @late_init: sets up late driver/hw state (post hw_init) - Optional
356  * @prepare_suspend: handle IP specific changes to prepare for suspend
358  * @suspend: handles IP specific hw/sw changes for suspend
359  * @resume: handles IP specific hw/sw changes for resume
360  * @is_idle: returns current IP block idle status
362  * @check_soft_reset: check soft reset the IP block
363  * @pre_soft_reset: pre soft reset the IP block
364  * @soft_reset: soft reset the IP block
365  * @post_soft_reset: post soft reset the IP block
366  * @set_clockgating_state: enable/disable cg for the IP block
367  * @set_powergating_state: enable/disable pg for the IP block
369  * @dump_ip_state: dump the IP state of the ASIC during a gpu hang
370  * @print_ip_state: print the IP state in devcoredump for each IP of the ASIC
373  * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
374  * the driver can make chip-wide state changes by walking this list and
375  * making calls to hooks from each IP block. This list is ordered to ensure
376  * that the driver initializes the IP blocks in a safe sequence.