459 struct dc;
464 	bool (*get_dcc_compression_cap)(const struct dc *dc,
467 	bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
480 /* Structure to hold configuration flags set by dm at dc creation. */
593  * default, DC favors MPC_SPLIT_DYNAMIC.
597 	 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
604 	 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
610 	 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
612 	 * user connects to a second display, DC will avoid pipe split.
645  * struct dc_clocks - DC pipe clocks
680 	 * DC has a mechanism that leverage the variable refresh rate to switch
682 	 * memory clock change and a short vblank window. DC has some
727 		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
728 				dm_get_timestamp(dc->ctx) : 0
731 		if (dc->debug.bw_val_profile.enable) \
732 			dc->debug.bw_val_profile.total_count++
735 		if (dc->debug.bw_val_profile.enable) { \
737 				voltage_level_tick = dm_get_timestamp(dc->ctx); \
738 			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
742 		if (dc->debug.bw_val_profile.enable) \
743 			voltage_level_tick = dm_get_timestamp(dc->ctx)
746 		if (dc->debug.bw_val_profile.enable) \
747 			watermark_tick = dm_get_timestamp(dc->ctx)
750 		if (dc->debug.bw_val_profile.enable) { \
751 			end_tick = dm_get_timestamp(dc->ctx); \
752 			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
753 			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
755 				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
756 				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
935  * struct dc_debug_options - DC debug struct
1170 /* Generic structure that can be used to query properties of DC. More fields
1233 struct dc *dc_create(const struct dc_init_data *init_params);
1234 void dc_hardware_init(struct dc *dc);
1236 int dc_get_vmid_use_vector(struct dc *dc);
1237 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1239 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1240 void dc_init_callbacks(struct dc *dc,
1242 void dc_deinit_callbacks(struct dc *dc);
1243 void dc_destroy(struct dc **dc);
1468 	/* private to DC core */
1522 	 * dc update. The reason is that plane states are overwritten
1523 	 * with surface updates in dc update. Once they are overwritten
1526 	 * a valid current state during dc update.
1629 	/* Private to DC core */
1631 	const struct dc *dc;  member
1701 struct dc {  struct
1865 		struct dc *dc);
1887 bool dc_validate_boot_timing(const struct dc *dc,
1891 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1893 enum dc_status dc_validate_with_context(struct dc *dc,
1903 		struct dc *dc,
1908 		struct dc *dc, bool acquire,
1913 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1930 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);
1933 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1938 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1955 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1958 bool dc_get_edp_link_panel_inst(const struct dc *dc,
1963 void dc_get_edp_links(const struct dc *dc,
1967 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
1981  * @reason - Indicate which event triggers this detection. dc may customize
2050  * handler once after no HPD change has been detected within dc default HPD
2054  * dc default HPD filtering interval since last HPD event.
2068 		struct dc *dc,
2078 		struct dc *dc,
2092 dc_get_oem_i2c_device(struct dc *dc);
2095 	struct dc *dc,
2103 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
2110  * true - Downstream port status changed. DM should call DC to do the
2193  * @dc: pointer to dc of the dm calling this
2194  * @map: a dc link resource snapshot defined internally to dc.
2206 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
2209  * @dc: pointer to dc of the dm calling this
2210  * @map: a dc link resource snapshot defined internally to dc.
2223 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
2231 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
2256  * channel coding format dc will choose.
2292 void dc_link_set_drive_settings(struct dc *dc,
2323 void dc_link_set_preferred_link_settings(struct dc *dc,
2333  * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2335  * passed in, dc resets previous overrides.
2339 void dc_link_set_preferred_training_settings(struct dc *dc,
2348 /* query FEC enablement policy to determine if FEC will be enabled by dc during
2462 /* Get how many link training attempts dc has done with latest sequence.
2506 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *…
2575 	/* private to DC core */
2609 		struct dc *dc,
2612 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2613 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2615 		struct dc *dc, uint32_t link_index);
2617 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2622 		struct dc *dc,
2624 void dc_resume(struct dc *dc);
2626 void dc_power_down_on_boot(struct dc *dc);
2635 bool dc_is_dmcu_initialized(struct dc *dc);
2637 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_…
2638 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2640 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
2646 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __fu…  argument
2647 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__)  argument
2649 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);
2650 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);
2651 bool dc_dmub_is_ips_idle_state(struct dc *dc);
2654 void dc_unlock_memory_clock_frequency(struct dc *dc);
2657 void dc_lock_memory_clock_frequency(struct dc *dc);
2659 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
2660 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2663 void dc_hardware_release(struct dc *dc);
2666 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2668 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2670 bool dc_set_replay_allow_active(struct dc *dc, bool active);
2672 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);
2674 void dc_z10_restore(const struct dc *dc);
2675 void dc_z10_save_init(struct dc *dc);
2677 bool dc_is_dmub_outbox_supported(struct dc *dc);
2678 bool dc_enable_dmub_notifications(struct dc *dc);
2681 		struct dc *dc,
2685 void dc_enable_dmub_outbox(struct dc *dc);
2687 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2691 /* Get dc link index from dpia port index */
2692 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2695 bool dc_process_dmub_set_config_async(struct dc *dc,
2700 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2705 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tp…
2707 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2710 void dc_print_dmub_diagnostic_data(const struct dc *dc);
2712 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
2728 	struct dc *dc,
2733 void dc_disable_accelerated_mode(struct dc *dc);
2738 bool dc_is_cursor_limit_pending(struct dc *dc);
2739 bool dc_can_clear_cursor_limit(struct dc *dc);
2744  * @dc: Pointer to the display core context.
2752 void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_d…