Lines Matching refs:uint8_t

52 	uint8_t		revision;
53 	uint8_t		checksum;
54 	uint8_t		oem_id[CRAT_OEMID_LENGTH];
55 	uint8_t		oem_table_id[CRAT_OEMTABLEID_LENGTH];
61 	uint8_t		reserved[CRAT_RESERVED_LENGTH];
99 	uint8_t		type;
100 	uint8_t		length;
111 	uint8_t		wave_front_size;
112 	uint8_t		num_banks;
114 	uint8_t		array_count;
115 	uint8_t		num_cu_per_array;
116 	uint8_t		num_simd_per_cu;
117 	uint8_t		max_slots_scatch_cu;
118 	uint8_t		reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
132 	uint8_t		type;
133 	uint8_t		length;
142 	uint8_t		visibility_type; /* for virtual (dGPU) CRAT */
143 	uint8_t		reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
159 	uint8_t		type;
160 	uint8_t		length;
164 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
166 	uint8_t		cache_level;
167 	uint8_t		lines_per_tag;
169 	uint8_t		associativity;
170 	uint8_t		cache_properties;
172 	uint8_t		reserved2[CRAT_CACHE_RESERVED_LENGTH];
188 	uint8_t		type;
189 	uint8_t		length;
193 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
195 	uint8_t		data_tlb_associativity_2mb;
196 	uint8_t		data_tlb_size_2mb;
197 	uint8_t		instruction_tlb_associativity_2mb;
198 	uint8_t		instruction_tlb_size_2mb;
199 	uint8_t		data_tlb_associativity_4k;
200 	uint8_t		data_tlb_size_4k;
201 	uint8_t		instruction_tlb_associativity_4k;
202 	uint8_t		instruction_tlb_size_4k;
203 	uint8_t		data_tlb_associativity_1gb;
204 	uint8_t		data_tlb_size_1gb;
205 	uint8_t		instruction_tlb_associativity_1gb;
206 	uint8_t		instruction_tlb_size_1gb;
207 	uint8_t		reserved2[CRAT_TLB_RESERVED_LENGTH];
219 	uint8_t		type;
220 	uint8_t		length;
224 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
226 	uint8_t		reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
265 	uint8_t		type;
266 	uint8_t		length;
271 	uint8_t		io_interface_type;
272 	uint8_t		version_major;
279 	uint8_t		reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];
280 	uint8_t		weight_xgmi;
290 	uint8_t		type;
291 	uint8_t		length;