Lines Matching +full:x +full:- +full:-
33 #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
34 #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
35 #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c)
36 #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c)
37 #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c)
38 #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c)
39 #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c)
42 #define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00)
43 #define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00)
44 #define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00)
45 #define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00)
46 #define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00)
47 #define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00)
48 #define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00)
49 #define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00)
50 #define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00)
53 #define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8)
54 #define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8)
55 #define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8)
56 #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8)
57 #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8)
58 #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8)
59 #define AUD6_REGISTER_OFFSET (0x17c0 - 0x17a8)
60 #define AUD7_REGISTER_OFFSET (0x17c4 - 0x17a8)
63 #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898)
64 #define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
65 #define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
66 #define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
67 #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
68 #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
70 #define PIPEID(x) ((x) << 0) argument
71 #define MEID(x) ((x) << 2) argument
72 #define VMID(x) ((x) << 4) argument
73 #define QUEUEID(x) ((x) << 8) argument
114 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
143 /* 0 - register
144 * 1 - memory (sync - via GRBM)
145 * 2 - gl2
146 * 3 - gds
147 * 4 - reserved
148 * 5 - memory (async - direct)
152 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) argument
153 /* 0 - LRU
154 * 1 - Stream
156 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
157 /* 0 - me
158 * 1 - pfp
159 * 2 - ce
165 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
169 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
170 /* 0 - always
171 * 1 - <
172 * 2 - <=
173 * 3 - ==
174 * 4 - !=
175 * 5 - >=
176 * 6 - >
178 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
179 /* 0 - reg
180 * 1 - mem
182 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) argument
183 /* 0 - wait_reg_mem
184 * 1 - wr_wait_wr_reg
186 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
187 /* 0 - me
188 * 1 - pfp
193 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) argument
194 /* 0 - LRU
195 * 1 - Stream
196 * 2 - Bypass
198 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) argument
227 #define EVENT_TYPE(x) ((x) << 0) argument
228 #define EVENT_INDEX(x) ((x) << 8) argument
229 /* 0 - any non-TS event
230 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
231 * 2 - SAMPLE_PIPELINESTAT
232 * 3 - SAMPLE_STREAMOUTSTAT*
233 * 4 - *S_PARTIAL_FLUSH
234 * 5 - EOP events
235 * 6 - EOS events
244 #define EOP_CACHE_POLICY(x) ((x) << 25) argument
245 /* 0 - LRU
246 * 1 - Stream
247 * 2 - Bypass
250 #define DATA_SEL(x) ((x) << 29) argument
251 /* 0 - discard
252 * 1 - send low 32bit data
253 * 2 - send 64bit data
254 * 3 - send 64bit GPU counter value
255 * 4 - send 64bit sys counter value
257 #define INT_SEL(x) ((x) << 24) argument
258 /* 0 - none
259 * 1 - interrupt only (DATA_SEL = 0)
260 * 2 - interrupt when data write is confirmed
262 #define DST_SEL(x) ((x) << 16) argument
263 /* 0 - MC
264 * 1 - TC/L2
281 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) argument
282 /* 0 - ME
283 * 1 - PFP
285 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) argument
286 /* 0 - LRU
287 * 1 - Stream
288 * 2 - Bypass
291 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) argument
292 /* 0 - DST_ADDR using DAS
293 * 1 - GDS
294 * 3 - DST_ADDR using L2
296 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) argument
297 /* 0 - LRU
298 * 1 - Stream
299 * 2 - Bypass
302 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) argument
303 /* 0 - SRC_ADDR using SAS
304 * 1 - GDS
305 * 2 - DATA
306 * 3 - SRC_ADDR using L2
311 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) argument
312 /* 0 - none
313 * 1 - 8 in 16
314 * 2 - 8 in 32
315 * 3 - 8 in 64
317 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) argument
318 /* 0 - none
319 * 1 - 8 in 16
320 * 2 - 8 in 32
321 * 3 - 8 in 64
324 /* 0 - memory
325 * 1 - register
328 /* 0 - memory
329 * 1 - register
366 # define FRAME_CMD(x) ((x) << 28) argument
368 * x=0: tmz_begin
369 * x=1: tmz_end
381 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) argument
382 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) argument
383 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) argument
394 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
395 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) argument
396 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) argument
397 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) argument
398 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
399 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
401 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) argument
402 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) argument
403 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 26) argument
404 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 29) argument
405 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 31) argument
415 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) argument
416 /* 0 - PREEMPT_QUEUES
417 * 1 - RESET_QUEUES
418 * 2 - DISABLE_PROCESS_QUEUES
419 * 3 - PREEMPT_QUEUES_NO_UNMAP
421 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
422 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
423 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
425 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) argument
427 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) argument
429 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) argument
431 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) argument
433 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) argument
435 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) argument
446 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) argument
447 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) argument
448 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) argument
450 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) argument
452 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) argument
453 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) argument
480 #define RB_MAP_PKR0(x) ((x) << 0) argument
482 #define RB_MAP_PKR1(x) ((x) << 2) argument
484 #define RB_XSEL2(x) ((x) << 4) argument
488 #define PKR_MAP(x) ((x) << 8) argument
490 #define PKR_XSEL(x) ((x) << 10) argument
492 #define PKR_YSEL(x) ((x) << 12) argument
494 #define SC_MAP(x) ((x) << 16) argument
496 #define SC_XSEL(x) ((x) << 18) argument
498 #define SC_YSEL(x) ((x) << 20) argument
500 #define SE_MAP(x) ((x) << 24) argument
502 #define SE_XSEL(x) ((x) << 26) argument
504 #define SE_YSEL(x) ((x) << 28) argument
508 #define SE_PAIR_MAP(x) ((x) << 0) argument
510 #define SE_PAIR_XSEL(x) ((x) << 2) argument
512 #define SE_PAIR_YSEL(x) ((x) << 4) argument