Lines Matching refs:ih_regs
57 struct amdgpu_ih_regs *ih_regs;
60 ih_regs = &adev->irq.ih.ih_regs;
61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
69 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
73 ih_regs = &adev->irq.ih1.ih_regs;
74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
75 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
76 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
79 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
80 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
84 ih_regs = &adev->irq.ih2.ih_regs;
85 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
86 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
87 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
89 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
90 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
91 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
108 struct amdgpu_ih_regs *ih_regs;
111 ih_regs = &ih->ih_regs;
113 tmp = RREG32(ih_regs->ih_rb_cntl);
123 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
126 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
132 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
135 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
148 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
153 WREG32(ih_regs->ih_rb_cntl, tmp);
160 WREG32(ih_regs->ih_rb_rptr, 0);
161 WREG32(ih_regs->ih_rb_wptr, 0);
247 struct amdgpu_ih_regs *ih_regs;
250 ih_regs = &ih->ih_regs;
253 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
254 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
256 tmp = RREG32(ih_regs->ih_rb_cntl);
263 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
268 WREG32(ih_regs->ih_rb_cntl, tmp);
273 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
274 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
278 WREG32(ih_regs->ih_rb_wptr, 0);
279 WREG32(ih_regs->ih_rb_rptr, 0);
281 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
420 struct amdgpu_ih_regs *ih_regs;
434 ih_regs = &ih->ih_regs;
437 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
455 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
457 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
463 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
481 struct amdgpu_ih_regs *ih_regs;
483 ih_regs = &ih->ih_regs;
487 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
506 struct amdgpu_ih_regs *ih_regs;
519 ih_regs = &ih->ih_regs;
520 WREG32(ih_regs->ih_rb_rptr, ih->rptr);