Lines Matching refs:ih_regs
49 struct amdgpu_ih_regs *ih_regs;
52 ih_regs = &adev->irq.ih.ih_regs;
53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
65 ih_regs = &adev->irq.ih1.ih_regs;
66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
76 ih_regs = &adev->irq.ih2.ih_regs;
77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
100 struct amdgpu_ih_regs *ih_regs;
103 ih_regs = &ih->ih_regs;
105 tmp = RREG32(ih_regs->ih_rb_cntl);
112 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
117 WREG32(ih_regs->ih_rb_cntl, tmp);
124 WREG32(ih_regs->ih_rb_rptr, 0);
125 WREG32(ih_regs->ih_rb_wptr, 0);
211 struct amdgpu_ih_regs *ih_regs;
214 ih_regs = &ih->ih_regs;
217 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
218 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
220 tmp = RREG32(ih_regs->ih_rb_cntl);
227 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
232 WREG32(ih_regs->ih_rb_cntl, tmp);
237 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
238 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
242 WREG32(ih_regs->ih_rb_wptr, 0);
243 WREG32(ih_regs->ih_rb_rptr, 0);
245 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih));
339 struct amdgpu_ih_regs *ih_regs;
353 ih_regs = &ih->ih_regs;
356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
371 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
373 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
379 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
397 struct amdgpu_ih_regs *ih_regs;
399 ih_regs = &ih->ih_regs;
402 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
421 struct amdgpu_ih_regs *ih_regs;
434 ih_regs = &ih->ih_regs;
435 WREG32(ih_regs->ih_rb_rptr, ih->rptr);