645 					bool indirect)  in vcn_v2_5_mc_resume_dpg_mode()  argument
654 		if (!indirect) {  in vcn_v2_5_mc_resume_dpg_mode()
657 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
660 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
662 				VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
665 				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
667 				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
669 				VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
675 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
678 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
682 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
685 	if (!indirect)  in vcn_v2_5_mc_resume_dpg_mode()
687 			VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
690 			VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
693 	if (!indirect) {  in vcn_v2_5_mc_resume_dpg_mode()
696 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
699 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
701 			VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
704 			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
706 			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
708 			VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
711 		VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
716 		lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
719 		upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
721 		VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
723 		VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
728 		lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
731 		upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
733 		VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
736 		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
740 		VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
860 		uint8_t sram_sel, uint8_t indirect)  in vcn_v2_5_clock_gating_dpg_mode()  argument
894 		VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
898 		VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
902 		VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
906 		VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
971 				bool indirect)  in vcn_v2_6_enable_ras()  argument
986 			      tmp, 0, indirect);  in vcn_v2_6_enable_ras()
991 			      tmp, 0, indirect);  in vcn_v2_6_enable_ras()
996 			      tmp, 0, indirect);  in vcn_v2_6_enable_ras()
999 static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)  in vcn_v2_5_start_dpg_mode()  argument
1017 	if (indirect)  in vcn_v2_5_start_dpg_mode()
1021 	vcn_v2_5_clock_gating_dpg_mode(vinst, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1028 		VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1032 		VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1044 		VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1048 		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1055 		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);  in vcn_v2_5_start_dpg_mode()
1062 		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);  in vcn_v2_5_start_dpg_mode()
1068 		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);  in vcn_v2_5_start_dpg_mode()
1070 	vcn_v2_5_mc_resume_dpg_mode(vinst, indirect);  in vcn_v2_5_start_dpg_mode()
1073 		VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1075 		VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1079 		VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1081 	vcn_v2_6_enable_ras(vinst, indirect);  in vcn_v2_5_start_dpg_mode()
1085 		VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1090 		VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1095 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);  in vcn_v2_5_start_dpg_mode()
1097 	if (indirect) {  in vcn_v2_5_start_dpg_mode()