179 	WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);  in vce_v4_0_mmsch_start()
180 	*adev->vce.ring[0].wptr_cpu_addr = 0;  in vce_v4_0_mmsch_start()
181 	adev->vce.ring[0].wptr = 0;  in vce_v4_0_mmsch_start()
182 	adev->vce.ring[0].wptr_old = 0;  in vce_v4_0_mmsch_start()
233 		ring = &adev->vce.ring[0];  in vce_v4_0_sriov_start()
263 						adev->vce.gpu_addr >> 8);  in vce_v4_0_sriov_start()
266 						(adev->vce.gpu_addr >> 40) & 0xff);  in vce_v4_0_sriov_start()
273 						adev->vce.gpu_addr >> 8);  in vce_v4_0_sriov_start()
276 						(adev->vce.gpu_addr >> 40) & 0xff);  in vce_v4_0_sriov_start()
279 						adev->vce.gpu_addr >> 8);  in vce_v4_0_sriov_start()
282 						(adev->vce.gpu_addr >> 40) & 0xff);  in vce_v4_0_sriov_start()
341 	ring = &adev->vce.ring[0];  in vce_v4_0_start()
349 	ring = &adev->vce.ring[1];  in vce_v4_0_start()
357 	ring = &adev->vce.ring[2];  in vce_v4_0_start()
415 		adev->vce.num_rings = 1;  in vce_v4_0_early_init()
417 		adev->vce.num_rings = 3;  in vce_v4_0_early_init()
433 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCE0, 167, &adev->vce.irq);  in vce_v4_0_sw_init()
447 		unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo);  in vce_v4_0_sw_init()
449 		adev->vce.saved_bo = kvmalloc(size, GFP_KERNEL);  in vce_v4_0_sw_init()
450 		if (!adev->vce.saved_bo)  in vce_v4_0_sw_init()
453 		hdr = (const struct common_firmware_header *)adev->vce.fw->data;  in vce_v4_0_sw_init()
455 		adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].fw = adev->vce.fw;  in vce_v4_0_sw_init()
465 	for (i = 0; i < adev->vce.num_rings; i++) {  in vce_v4_0_sw_init()
468 		ring = &adev->vce.ring[i];  in vce_v4_0_sw_init()
483 		r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,  in vce_v4_0_sw_init()
505 		kvfree(adev->vce.saved_bo);  in vce_v4_0_sw_fini()
506 		adev->vce.saved_bo = NULL;  in vce_v4_0_sw_fini()
528 	for (i = 0; i < adev->vce.num_rings; i++) {  in vce_v4_0_hw_init()
529 		r = amdgpu_ring_test_helper(&adev->vce.ring[i]);  in vce_v4_0_hw_init()
543 	cancel_delayed_work_sync(&adev->vce.idle_work);  in vce_v4_0_hw_fini()
561 	if (adev->vce.vcpu_bo == NULL)  in vce_v4_0_suspend()
566 			unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo);  in vce_v4_0_suspend()
567 			void *ptr = adev->vce.cpu_addr;  in vce_v4_0_suspend()
569 			memcpy_fromio(adev->vce.saved_bo, ptr, size);  in vce_v4_0_suspend()
585 	cancel_delayed_work_sync(&adev->vce.idle_work);  in vce_v4_0_suspend()
609 	if (adev->vce.vcpu_bo == NULL)  in vce_v4_0_resume()
615 			unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo);  in vce_v4_0_resume()
616 			void *ptr = adev->vce.cpu_addr;  in vce_v4_0_resume()
618 			memcpy_toio(ptr, adev->vce.saved_bo, size);  in vce_v4_0_resume()
658 			(adev->vce.gpu_addr >> 8));  in vce_v4_0_mc_resume()
660 			(adev->vce.gpu_addr >> 40) & 0xff);  in vce_v4_0_mc_resume()
667 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8));  in vce_v4_0_mc_resume()
668 …WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xf…  in vce_v4_0_mc_resume()
674 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8));  in vce_v4_0_mc_resume()
675 …WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xf…  in vce_v4_0_mc_resume()
798 		amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);  in vce_v4_0_process_interrupt()
858 	for (i = 0; i < adev->vce.num_rings; i++) {  in vce_v4_0_set_ring_funcs()
859 		adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs;  in vce_v4_0_set_ring_funcs()
860 		adev->vce.ring[i].me = i;  in vce_v4_0_set_ring_funcs()
872 	adev->vce.irq.num_types = 1;  in vce_v4_0_set_irq_funcs()
873 	adev->vce.irq.funcs = &vce_v4_0_irq_funcs;  in vce_v4_0_set_irq_funcs()