199 	hdr = (const struct common_firmware_header *)adev->vce.fw->data;  in vce_v1_0_load_fw()
202 	cpu_addr = adev->vce.cpu_addr;  in vce_v1_0_load_fw()
204 	sign = (void *)adev->vce.fw->data + ucode_offset;  in vce_v1_0_load_fw()
235 	memset_io(&cpu_addr[0], 0, amdgpu_bo_size(adev->vce.vcpu_bo));  in vce_v1_0_load_fw()
247 	adev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);  in vce_v1_0_load_fw()
256 	dev_dbg(adev->dev, "VCE keyselect: %d", adev->vce.keyselect);  in vce_v1_0_wait_for_fw_validation()
257 	WREG32(mmVCE_LMI_FW_START_KEYSEL, adev->vce.keyselect);  in vce_v1_0_wait_for_fw_validation()
300 			RREG32(mmVCE_LMI_FW_START_KEYSEL), adev->vce.keyselect);  in vce_v1_0_mc_resume()
322 	offset =  adev->vce.gpu_addr + AMDGPU_VCE_FIRMWARE_OFFSET;  in vce_v1_0_mc_resume()
338 	WARN_ON((offset + size - adev->vce.gpu_addr) > amdgpu_bo_size(adev->vce.vcpu_bo));  in vce_v1_0_mc_resume()
398 	ring = &adev->vce.ring[0];  in vce_v1_0_start()
405 	ring = &adev->vce.ring[1];  in vce_v1_0_start()
522 	adev->vce.num_rings = 2;  in vce_v1_0_early_init()
550 	u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo);  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
553 	u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo);  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
559 		return amdgpu_bo_gpu_offset(adev->vce.vcpu_bo) <= max_vcpu_bo_addr ? 0 : -EINVAL;  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
561 	if (!drm_mm_node_allocated(&adev->vce.gart_node)) {  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
563 						 &adev->vce.gart_node, num_pages,  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
569 	vce_gart_start_offs = amdgpu_gtt_node_to_byte_offset(&adev->vce.gart_node);  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
575 	amdgpu_gart_map_vram_range(adev, pa, adev->vce.gart_node.start,  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
577 	adev->vce.gpu_addr = adev->gmc.gart_start + vce_gart_start_offs;  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
588 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq);  in vce_v1_0_sw_init()
604 	for (i = 0; i < adev->vce.num_rings; i++) {  in vce_v1_0_sw_init()
607 		ring = &adev->vce.ring[i];  in vce_v1_0_sw_init()
609 		r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,  in vce_v1_0_sw_init()
629 	amdgpu_gtt_mgr_free_entries(&adev->mman.gtt_mgr, &adev->vce.gart_node);  in vce_v1_0_sw_fini()
651 	for (i = 0; i < adev->vce.num_rings; i++) {  in vce_v1_0_hw_init()
652 		r = amdgpu_ring_test_helper(&adev->vce.ring[i]);  in vce_v1_0_hw_init()
670 	cancel_delayed_work_sync(&ip_block->adev->vce.idle_work);  in vce_v1_0_hw_fini()
690 	cancel_delayed_work_sync(&adev->vce.idle_work);  in vce_v1_0_suspend()
749 		amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);  in vce_v1_0_process_interrupt()
831 	for (i = 0; i < adev->vce.num_rings; i++) {  in vce_v1_0_set_ring_funcs()
832 		adev->vce.ring[i].funcs = &vce_v1_0_ring_funcs;  in vce_v1_0_set_ring_funcs()
833 		adev->vce.ring[i].me = i;  in vce_v1_0_set_ring_funcs()
844 	adev->vce.irq.num_types = 1;  in vce_v1_0_set_irq_funcs()
845 	adev->vce.irq.funcs = &vce_v1_0_irq_funcs;  in vce_v1_0_set_irq_funcs()