51 static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev);
52 static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev);
75 	struct amdgpu_device *adev = ring->adev;  in vce_v1_0_ring_get_rptr()  local
92 	struct amdgpu_device *adev = ring->adev;  in vce_v1_0_ring_get_wptr()  local
109 	struct amdgpu_device *adev = ring->adev;  in vce_v1_0_ring_set_wptr()  local
117 static int vce_v1_0_lmi_clean(struct amdgpu_device *adev)  in vce_v1_0_lmi_clean()  argument
133 static int vce_v1_0_firmware_loaded(struct amdgpu_device *adev)  in vce_v1_0_firmware_loaded()  argument
144 		dev_err(adev->dev, "VCE not responding, trying to reset the ECPU\n");  in vce_v1_0_firmware_loaded()
158 static void vce_v1_0_init_cg(struct amdgpu_device *adev)  in vce_v1_0_init_cg()  argument
189 static int vce_v1_0_load_fw(struct amdgpu_device *adev)  in vce_v1_0_load_fw()  argument
199 	hdr = (const struct common_firmware_header *)adev->vce.fw->data;  in vce_v1_0_load_fw()
202 	cpu_addr = adev->vce.cpu_addr;  in vce_v1_0_load_fw()
204 	sign = (void *)adev->vce.fw->data + ucode_offset;  in vce_v1_0_load_fw()
209 	switch (adev->asic_type) {  in vce_v1_0_load_fw()
220 		dev_err(adev->dev, "asic_type %#010x was not found!", adev->asic_type);  in vce_v1_0_load_fw()
230 		dev_err(adev->dev, "chip_id 0x%x for %s was not found in VCE firmware",  in vce_v1_0_load_fw()
231 			chip_id, amdgpu_asic_name[adev->asic_type]);  in vce_v1_0_load_fw()
235 	memset_io(&cpu_addr[0], 0, amdgpu_bo_size(adev->vce.vcpu_bo));  in vce_v1_0_load_fw()
247 	adev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);  in vce_v1_0_load_fw()
252 static int vce_v1_0_wait_for_fw_validation(struct amdgpu_device *adev)  in vce_v1_0_wait_for_fw_validation()  argument
256 	dev_dbg(adev->dev, "VCE keyselect: %d", adev->vce.keyselect);  in vce_v1_0_wait_for_fw_validation()
257 	WREG32(mmVCE_LMI_FW_START_KEYSEL, adev->vce.keyselect);  in vce_v1_0_wait_for_fw_validation()
266 		dev_err(adev->dev, "VCE FW validation timeout\n");  in vce_v1_0_wait_for_fw_validation()
271 		dev_err(adev->dev, "VCE FW validation failed\n");  in vce_v1_0_wait_for_fw_validation()
282 		dev_err(adev->dev, "VCE FW busy timeout\n");  in vce_v1_0_wait_for_fw_validation()
289 static int vce_v1_0_mc_resume(struct amdgpu_device *adev)  in vce_v1_0_mc_resume()  argument
299 		dev_dbg(adev->dev, "keyselect already set: 0x%x (on CPU: 0x%x)\n",  in vce_v1_0_mc_resume()
300 			RREG32(mmVCE_LMI_FW_START_KEYSEL), adev->vce.keyselect);  in vce_v1_0_mc_resume()
322 	offset =  adev->vce.gpu_addr + AMDGPU_VCE_FIRMWARE_OFFSET;  in vce_v1_0_mc_resume()
338 	WARN_ON((offset + size - adev->vce.gpu_addr) > amdgpu_bo_size(adev->vce.vcpu_bo));  in vce_v1_0_mc_resume()
344 	return vce_v1_0_wait_for_fw_validation(adev);  in vce_v1_0_mc_resume()
359 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_is_idle()  local
369 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_wait_for_idle()  local
372 	for (i = 0; i < adev->usec_timeout; i++) {  in vce_v1_0_wait_for_idle()
387 static int vce_v1_0_start(struct amdgpu_device *adev)  in vce_v1_0_start()  argument
394 	r = vce_v1_0_mc_resume(adev);  in vce_v1_0_start()
398 	ring = &adev->vce.ring[0];  in vce_v1_0_start()
405 	ring = &adev->vce.ring[1];  in vce_v1_0_start()
427 	r = vce_v1_0_firmware_loaded(adev);  in vce_v1_0_start()
433 		dev_err(adev->dev, "VCE not responding, giving up\n");  in vce_v1_0_start()
440 static int vce_v1_0_stop(struct amdgpu_device *adev)  in vce_v1_0_stop()  argument
446 	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE);  in vce_v1_0_stop()
450 	if (vce_v1_0_lmi_clean(adev))  in vce_v1_0_stop()
451 		dev_warn(adev->dev, "VCE not idle\n");  in vce_v1_0_stop()
454 		dev_warn(adev->dev, "VCE busy: VCE_STATUS=0x%x, SRBM_STATUS2=0x%x\n",  in vce_v1_0_stop()
480 static void vce_v1_0_enable_mgcg(struct amdgpu_device *adev, bool enable)  in vce_v1_0_enable_mgcg()  argument
484 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {  in vce_v1_0_enable_mgcg()
515 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_early_init()  local
518 	r = amdgpu_vce_early_init(adev);  in vce_v1_0_early_init()
522 	adev->vce.num_rings = 2;  in vce_v1_0_early_init()
524 	vce_v1_0_set_ring_funcs(adev);  in vce_v1_0_early_init()
525 	vce_v1_0_set_irq_funcs(adev);  in vce_v1_0_early_init()
548 static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev)  in vce_v1_0_ensure_vcpu_bo_32bit_addr()  argument
550 	u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo);  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
553 	u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo);  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
558 	if (adev->gmc.vram_start < adev->gmc.gart_start)  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
559 		return amdgpu_bo_gpu_offset(adev->vce.vcpu_bo) <= max_vcpu_bo_addr ? 0 : -EINVAL;  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
561 	if (!drm_mm_node_allocated(&adev->vce.gart_node)) {  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
562 		r = amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr,  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
563 						 &adev->vce.gart_node, num_pages,  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
569 	vce_gart_start_offs = amdgpu_gtt_node_to_byte_offset(&adev->vce.gart_node);  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
572 	if (adev->gmc.gart_start + vce_gart_start_offs > max_vcpu_bo_addr)  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
575 	amdgpu_gart_map_vram_range(adev, pa, adev->vce.gart_node.start,  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
576 				   num_pages, flags, adev->gart.ptr);  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
577 	adev->vce.gpu_addr = adev->gmc.gart_start + vce_gart_start_offs;  in vce_v1_0_ensure_vcpu_bo_32bit_addr()
584 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_sw_init()  local
588 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq);  in vce_v1_0_sw_init()
592 	r = amdgpu_vce_sw_init(adev, VCE_V1_0_FW_SIZE +  in vce_v1_0_sw_init()
597 	r = vce_v1_0_load_fw(adev);  in vce_v1_0_sw_init()
600 	r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev);  in vce_v1_0_sw_init()
604 	for (i = 0; i < adev->vce.num_rings; i++) {  in vce_v1_0_sw_init()
607 		ring = &adev->vce.ring[i];  in vce_v1_0_sw_init()
609 		r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,  in vce_v1_0_sw_init()
620 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_sw_fini()  local
623 	r = amdgpu_vce_suspend(adev);  in vce_v1_0_sw_fini()
627 	r = amdgpu_vce_sw_fini(adev);  in vce_v1_0_sw_fini()
629 	amdgpu_gtt_mgr_free_entries(&adev->mman.gtt_mgr, &adev->vce.gart_node);  in vce_v1_0_sw_fini()
643 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_hw_init()  local
646 	if (adev->pm.dpm_enabled)  in vce_v1_0_hw_init()
647 		amdgpu_dpm_enable_vce(adev, true);  in vce_v1_0_hw_init()
649 		amdgpu_asic_set_vce_clocks(adev, 10000, 10000);  in vce_v1_0_hw_init()
651 	for (i = 0; i < adev->vce.num_rings; i++) {  in vce_v1_0_hw_init()
652 		r = amdgpu_ring_test_helper(&adev->vce.ring[i]);  in vce_v1_0_hw_init()
657 	dev_info(adev->dev, "VCE initialized successfully.\n");  in vce_v1_0_hw_init()
666 	r = vce_v1_0_stop(ip_block->adev);  in vce_v1_0_hw_fini()
670 	cancel_delayed_work_sync(&ip_block->adev->vce.idle_work);  in vce_v1_0_hw_fini()
676 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_suspend()  local
690 	cancel_delayed_work_sync(&adev->vce.idle_work);  in vce_v1_0_suspend()
692 	if (adev->pm.dpm_enabled) {  in vce_v1_0_suspend()
693 		amdgpu_dpm_enable_vce(adev, false);  in vce_v1_0_suspend()
695 		amdgpu_asic_set_vce_clocks(adev, 0, 0);  in vce_v1_0_suspend()
696 		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,  in vce_v1_0_suspend()
698 		amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,  in vce_v1_0_suspend()
704 		dev_err(adev->dev, "vce_v1_0_hw_fini() failed with error %i", r);  in vce_v1_0_suspend()
708 	return amdgpu_vce_suspend(adev);  in vce_v1_0_suspend()
713 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_resume()  local
716 	r = vce_v1_0_load_fw(adev);  in vce_v1_0_resume()
719 	r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev);  in vce_v1_0_resume()
726 static int vce_v1_0_set_interrupt_state(struct amdgpu_device *adev,  in vce_v1_0_set_interrupt_state()  argument
741 static int vce_v1_0_process_interrupt(struct amdgpu_device *adev,  in vce_v1_0_process_interrupt()  argument
745 	dev_dbg(adev->dev, "IH: VCE\n");  in vce_v1_0_process_interrupt()
749 		amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);  in vce_v1_0_process_interrupt()
752 		dev_err(adev->dev, "Unhandled interrupt: %d %d\n",  in vce_v1_0_process_interrupt()
763 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_set_clockgating_state()  local
765 	vce_v1_0_init_cg(adev);  in vce_v1_0_set_clockgating_state()
766 	vce_v1_0_enable_mgcg(adev, state == AMD_CG_STATE_GATE);  in vce_v1_0_set_clockgating_state()
774 	struct amdgpu_device *adev = ip_block->adev;  in vce_v1_0_set_powergating_state()  local
785 		return vce_v1_0_stop(adev);  in vce_v1_0_set_powergating_state()
787 		return vce_v1_0_start(adev);  in vce_v1_0_set_powergating_state()
827 static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev)  in vce_v1_0_set_ring_funcs()  argument
831 	for (i = 0; i < adev->vce.num_rings; i++) {  in vce_v1_0_set_ring_funcs()
832 		adev->vce.ring[i].funcs = &vce_v1_0_ring_funcs;  in vce_v1_0_set_ring_funcs()
833 		adev->vce.ring[i].me = i;  in vce_v1_0_set_ring_funcs()
842 static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev)  in vce_v1_0_set_irq_funcs()  argument
844 	adev->vce.irq.num_types = 1;  in vce_v1_0_set_irq_funcs()
845 	adev->vce.irq.funcs = &vce_v1_0_irq_funcs;  in vce_v1_0_set_irq_funcs()