89 	if (ring == &adev->uvd.inst[ring->me].ring_enc[0])  in uvd_v7_0_enc_ring_get_rptr()
123 	if (ring == &adev->uvd.inst[ring->me].ring_enc[0])  in uvd_v7_0_enc_ring_get_wptr()
161 	if (ring == &adev->uvd.inst[ring->me].ring_enc[0])  in uvd_v7_0_enc_ring_set_wptr()
342 	struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;  in uvd_v7_0_enc_ring_test_ib()
372 		adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;  in uvd_v7_0_early_init()
373 		for (i = 0; i < adev->uvd.num_uvd_inst; i++) {  in uvd_v7_0_early_init()
376 				adev->uvd.harvest_config |= 1 << i;  in uvd_v7_0_early_init()
379 		if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 |  in uvd_v7_0_early_init()
384 		adev->uvd.num_uvd_inst = 1;  in uvd_v7_0_early_init()
388 		adev->uvd.num_enc_rings = 1;  in uvd_v7_0_early_init()
390 		adev->uvd.num_enc_rings = 2;  in uvd_v7_0_early_init()
405 	for (j = 0; j < adev->uvd.num_uvd_inst; j++) {  in uvd_v7_0_sw_init()
406 		if (adev->uvd.harvest_config & (1 << j))  in uvd_v7_0_sw_init()
409 … amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);  in uvd_v7_0_sw_init()
414 		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {  in uvd_v7_0_sw_init()
415 …id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);  in uvd_v7_0_sw_init()
427 		hdr = (const struct common_firmware_header *)adev->uvd.fw->data;  in uvd_v7_0_sw_init()
429 		adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;  in uvd_v7_0_sw_init()
433 		if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) {  in uvd_v7_0_sw_init()
435 			adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw;  in uvd_v7_0_sw_init()
442 	for (j = 0; j < adev->uvd.num_uvd_inst; j++) {  in uvd_v7_0_sw_init()
443 		if (adev->uvd.harvest_config & (1 << j))  in uvd_v7_0_sw_init()
446 			ring = &adev->uvd.inst[j].ring;  in uvd_v7_0_sw_init()
450 					     &adev->uvd.inst[j].irq, 0,  in uvd_v7_0_sw_init()
456 		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {  in uvd_v7_0_sw_init()
457 			ring = &adev->uvd.inst[j].ring_enc[i];  in uvd_v7_0_sw_init()
472 					     &adev->uvd.inst[j].irq, 0,  in uvd_v7_0_sw_init()
501 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {  in uvd_v7_0_sw_fini()
502 		if (adev->uvd.harvest_config & (1 << j))  in uvd_v7_0_sw_fini()
504 		for (i = 0; i < adev->uvd.num_enc_rings; ++i)  in uvd_v7_0_sw_fini()
505 			amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);  in uvd_v7_0_sw_fini()
531 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {  in uvd_v7_0_hw_init()
532 		if (adev->uvd.harvest_config & (1 << j))  in uvd_v7_0_hw_init()
534 		ring = &adev->uvd.inst[j].ring;  in uvd_v7_0_hw_init()
574 		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {  in uvd_v7_0_hw_init()
575 			ring = &adev->uvd.inst[j].ring_enc[i];  in uvd_v7_0_hw_init()
599 	cancel_delayed_work_sync(&adev->uvd.idle_work);  in uvd_v7_0_hw_fini()
634 	cancel_delayed_work_sync(&adev->uvd.idle_work);  in uvd_v7_0_suspend()
678 	for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {  in uvd_v7_0_mc_resume()
679 		if (adev->uvd.harvest_config & (1 << i))  in uvd_v7_0_mc_resume()
694 				lower_32_bits(adev->uvd.inst[i].gpu_addr));  in uvd_v7_0_mc_resume()
696 				upper_32_bits(adev->uvd.inst[i].gpu_addr));  in uvd_v7_0_mc_resume()
705 				lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));  in uvd_v7_0_mc_resume()
707 				upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));  in uvd_v7_0_mc_resume()
712 				lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));  in uvd_v7_0_mc_resume()
714 				upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));  in uvd_v7_0_mc_resume()
726 		WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);  in uvd_v7_0_mc_resume()
757 	for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {  in uvd_v7_0_mmsch_start()
758 		if (adev->uvd.harvest_config & (1 << i))  in uvd_v7_0_mmsch_start()
760 		WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);  in uvd_v7_0_mmsch_start()
761 		*adev->uvd.inst[i].ring_enc[0].wptr_cpu_addr = 0;  in uvd_v7_0_mmsch_start()
762 		adev->uvd.inst[i].ring_enc[0].wptr = 0;  in uvd_v7_0_mmsch_start()
763 		adev->uvd.inst[i].ring_enc[0].wptr_old = 0;  in uvd_v7_0_mmsch_start()
815 		for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {  in uvd_v7_0_sriov_start()
816 			if (adev->uvd.harvest_config & (1 << i))  in uvd_v7_0_sriov_start()
818 			ring = &adev->uvd.inst[i].ring;  in uvd_v7_0_sriov_start()
820 			size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);  in uvd_v7_0_sriov_start()
836 							    lower_32_bits(adev->uvd.inst[i].gpu_addr));  in uvd_v7_0_sriov_start()
838 							    upper_32_bits(adev->uvd.inst[i].gpu_addr));  in uvd_v7_0_sriov_start()
848 						    lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));  in uvd_v7_0_sriov_start()
850 						    upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));  in uvd_v7_0_sriov_start()
855 						    lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));  in uvd_v7_0_sriov_start()
857 						    upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));  in uvd_v7_0_sriov_start()
862 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);  in uvd_v7_0_sriov_start()
921 			ring = &adev->uvd.inst[i].ring_enc[0];  in uvd_v7_0_sriov_start()
960 	for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {  in uvd_v7_0_start()
961 		if (adev->uvd.harvest_config & (1 << k))  in uvd_v7_0_start()
974 	for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {  in uvd_v7_0_start()
975 		if (adev->uvd.harvest_config & (1 << k))  in uvd_v7_0_start()
977 		ring = &adev->uvd.inst[k].ring;  in uvd_v7_0_start()
1115 		ring = &adev->uvd.inst[k].ring_enc[0];  in uvd_v7_0_start()
1122 		ring = &adev->uvd.inst[k].ring_enc[1];  in uvd_v7_0_start()
1143 	for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {  in uvd_v7_0_stop()
1144 		if (adev->uvd.harvest_config & (1 << i))  in uvd_v7_0_stop()
1496 		amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);  in uvd_v7_0_process_interrupt()
1499 		amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);  in uvd_v7_0_process_interrupt()
1503 			amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);  in uvd_v7_0_process_interrupt()
1602 	for (i = 0; i < adev->uvd.num_uvd_inst; i++) {  in uvd_v7_0_set_ring_funcs()
1603 		if (adev->uvd.harvest_config & (1 << i))  in uvd_v7_0_set_ring_funcs()
1605 		adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;  in uvd_v7_0_set_ring_funcs()
1606 		adev->uvd.inst[i].ring.me = i;  in uvd_v7_0_set_ring_funcs()
1615 	for (j = 0; j < adev->uvd.num_uvd_inst; j++) {  in uvd_v7_0_set_enc_ring_funcs()
1616 		if (adev->uvd.harvest_config & (1 << j))  in uvd_v7_0_set_enc_ring_funcs()
1618 		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {  in uvd_v7_0_set_enc_ring_funcs()
1619 			adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;  in uvd_v7_0_set_enc_ring_funcs()
1620 			adev->uvd.inst[j].ring_enc[i].me = j;  in uvd_v7_0_set_enc_ring_funcs()
1636 	for (i = 0; i < adev->uvd.num_uvd_inst; i++) {  in uvd_v7_0_set_irq_funcs()
1637 		if (adev->uvd.harvest_config & (1 << i))  in uvd_v7_0_set_irq_funcs()
1639 		adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;  in uvd_v7_0_set_irq_funcs()
1640 		adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;  in uvd_v7_0_set_irq_funcs()