Lines Matching refs:uvd
96 adev->uvd.num_uvd_inst = 1; in uvd_v4_2_early_init()
111 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); in uvd_v4_2_sw_init()
119 ring = &adev->uvd.inst->ring; in uvd_v4_2_sw_init()
121 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, in uvd_v4_2_sw_init()
157 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v4_2_hw_init()
213 cancel_delayed_work_sync(&adev->uvd.idle_work); in uvd_v4_2_hw_fini()
244 cancel_delayed_work_sync(&adev->uvd.idle_work); in uvd_v4_2_suspend()
284 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v4_2_start()
579 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v4_2_mc_resume()
591 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v4_2_mc_resume()
596 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; in uvd_v4_2_mc_resume()
600 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; in uvd_v4_2_mc_resume()
707 amdgpu_fence_process(&adev->uvd.inst->ring); in uvd_v4_2_process_interrupt()
796 adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs; in uvd_v4_2_set_ring_funcs()
806 adev->uvd.inst->irq.num_types = 1; in uvd_v4_2_set_irq_funcs()
807 adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs; in uvd_v4_2_set_irq_funcs()