38  * Starting with r6xx, interrupts are handled via a ring buffer.
45  * writes vectors to the ring buffer, it increments the
54  * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
58  * Enable the interrupt ring buffer (VI).
67 	adev->irq.ih.enabled = true;  in tonga_ih_enable_interrupts()
71  * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
75  * Disable the interrupt ring buffer (VI).
87 	adev->irq.ih.enabled = false;  in tonga_ih_disable_interrupts()
88 	adev->irq.ih.rptr = 0;  in tonga_ih_disable_interrupts()
92  * tonga_ih_irq_init - init and enable the interrupt ring
96  * Allocate a ring buffer for the interrupt controller,
97  * enable the RLC, disable interrupts, enable the IH
98  * ring buffer and enable it (VI).
105 	struct amdgpu_ih_ring *ih = &adev->irq.ih;  in tonga_ih_irq_init()
112 	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);  in tonga_ih_irq_init()
114 	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi  in tonga_ih_irq_init()
115 	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN  in tonga_ih_irq_init()
118 	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */  in tonga_ih_irq_init()
122 	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/  in tonga_ih_irq_init()
123 	WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);  in tonga_ih_irq_init()
125 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);  in tonga_ih_irq_init()
128 …/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory…  in tonga_ih_irq_init()
132 	if (adev->irq.msi_enabled)  in tonga_ih_irq_init()
138 	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));  in tonga_ih_irq_init()
139 	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);  in tonga_ih_irq_init()
146 	if (adev->irq.ih.use_doorbell) {  in tonga_ih_irq_init()
148 						 OFFSET, adev->irq.ih.doorbell_index);  in tonga_ih_irq_init()
150 						 ENABLE, 1);  in tonga_ih_irq_init()
153 						 ENABLE, 0);  in tonga_ih_irq_init()
157 	pci_set_master(adev->pdev);  in tonga_ih_irq_init()
159 	/* enable interrupts */  in tonga_ih_irq_init()
162 	if (adev->irq.ih_soft.ring_size)  in tonga_ih_irq_init()
163 		adev->irq.ih_soft.enabled = true;  in tonga_ih_irq_init()
169  * tonga_ih_irq_disable - disable interrupts
184  * tonga_ih_get_wptr - get the IH ring buffer wptr
187  * @ih: IH ring buffer to fetch wptr
189  * Get the IH ring buffer wptr from either the register
190  * or the writeback memory buffer (VI).  Also check for
191  * ring buffer overflow and deal with it.
200 	wptr = le32_to_cpu(*ih->wptr_cpu);  in tonga_ih_get_wptr()
202 	if (ih == &adev->irq.ih_soft)  in tonga_ih_get_wptr()
216 	/* When a ring buffer overflow happen start parsing interrupt  in tonga_ih_get_wptr()
221 	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",  in tonga_ih_get_wptr()
222 		wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);  in tonga_ih_get_wptr()
223 	ih->rptr = (wptr + 16) & ih->ptr_mask;  in tonga_ih_get_wptr()
235 	return (wptr & ih->ptr_mask);  in tonga_ih_get_wptr()
239  * tonga_ih_decode_iv - decode an interrupt vector
242  * @ih: IH ring buffer to decode
253 	u32 ring_index = ih->rptr >> 2;  in tonga_ih_decode_iv()
256 	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);  in tonga_ih_decode_iv()
257 	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);  in tonga_ih_decode_iv()
258 	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);  in tonga_ih_decode_iv()
259 	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);  in tonga_ih_decode_iv()
261 	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;  in tonga_ih_decode_iv()
262 	entry->src_id = dw[0] & 0xff;  in tonga_ih_decode_iv()
263 	entry->src_data[0] = dw[1] & 0xfffffff;  in tonga_ih_decode_iv()
264 	entry->ring_id = dw[2] & 0xff;  in tonga_ih_decode_iv()
265 	entry->vmid = (dw[2] >> 8) & 0xff;  in tonga_ih_decode_iv()
266 	entry->pasid = (dw[2] >> 16) & 0xffff;  in tonga_ih_decode_iv()
269 	ih->rptr += 16;  in tonga_ih_decode_iv()
273  * tonga_ih_set_rptr - set the IH ring buffer rptr
276  * @ih: IH ring buffer to set rptr
278  * Set the IH ring buffer rptr.
283 	if (ih->use_doorbell) {  in tonga_ih_set_rptr()
285 		*ih->rptr_cpu = ih->rptr;  in tonga_ih_set_rptr()
286 		WDOORBELL32(ih->doorbell_index, ih->rptr);  in tonga_ih_set_rptr()
288 		WREG32(mmIH_RB_RPTR, ih->rptr);  in tonga_ih_set_rptr()
294 	struct amdgpu_device *adev = ip_block->adev;  in tonga_ih_early_init()
309 	struct amdgpu_device *adev = ip_block->adev;  in tonga_ih_sw_init()
311 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);  in tonga_ih_sw_init()
315 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);  in tonga_ih_sw_init()
319 	adev->irq.ih.use_doorbell = true;  in tonga_ih_sw_init()
320 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih;  in tonga_ih_sw_init()
329 	struct amdgpu_device *adev = ip_block->adev;  in tonga_ih_sw_fini()
340 	struct amdgpu_device *adev = ip_block->adev;  in tonga_ih_hw_init()
351 	tonga_ih_irq_disable(ip_block->adev);  in tonga_ih_hw_fini()
368 	struct amdgpu_device *adev = ip_block->adev;  in tonga_ih_is_idle()
381 	struct amdgpu_device *adev = ip_block->adev;  in tonga_ih_wait_for_idle()
383 	for (i = 0; i < adev->usec_timeout; i++) {  in tonga_ih_wait_for_idle()
390 	return -ETIMEDOUT;  in tonga_ih_wait_for_idle()
395 	struct amdgpu_device *adev = ip_block->adev;  in tonga_ih_check_soft_reset()
404 		adev->irq.srbm_soft_reset = srbm_soft_reset;  in tonga_ih_check_soft_reset()
407 		adev->irq.srbm_soft_reset = 0;  in tonga_ih_check_soft_reset()
414 	if (!ip_block->adev->irq.srbm_soft_reset)  in tonga_ih_pre_soft_reset()
422 	struct amdgpu_device *adev = ip_block->adev;  in tonga_ih_post_soft_reset()
424 	if (!adev->irq.srbm_soft_reset)  in tonga_ih_post_soft_reset()
432 	struct amdgpu_device *adev = ip_block->adev;  in tonga_ih_soft_reset()
435 	if (!adev->irq.srbm_soft_reset)  in tonga_ih_soft_reset()
437 	srbm_soft_reset = adev->irq.srbm_soft_reset;  in tonga_ih_soft_reset()
444 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in tonga_ih_soft_reset()
500 	adev->irq.ih_funcs = &tonga_ih_funcs;  in tonga_ih_set_interrupt_funcs()