28 #define GET_INST(ip, inst) \  argument
31 #define GET_MASK(ip, mask) \  argument
36 #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)  argument
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \  argument
50 #define WREG32_FIELD15(ip, idx, reg, field, val)	\  argument
58 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val)        \  argument
66 #define RREG32_SOC15(ip, inst, reg) \  argument
70 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0)  argument
72 #define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HW…  argument
74 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \  argument
78 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \  argument
82 #define WREG32_SOC15(ip, inst, reg, value) \  argument
86 #define WREG32_SOC15_IP(ip, reg, value) \  argument
89 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \  argument
92 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \  argument
96 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \  argument
100 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask)      \  argument
105 #define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask)  \  argument
138 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \  argument
151 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \  argument
169 #define RREG32_SOC15_RLC(ip, inst, reg) \  argument
172 #define WREG32_SOC15_RLC(ip, inst, reg, value) \  argument
178 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \  argument
184 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \  argument
191 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \  argument
194 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \  argument
198 #define RREG32_SOC15_EXT(ip, inst, reg, ext) \  argument
202 #define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \  argument