61 	mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
62 	mmCB_HW_CONTROL, 0x00010000, 0x00018208,
63 	mmDB_DEBUG, 0xffffffff, 0x00000000,
64 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
65 	mmDB_DEBUG3, 0x0002021c, 0x00020200,
66 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
67 	0x340c, 0x000000c0, 0x00800040,
68 	0x360c, 0x000000c0, 0x00800040,
69 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
70 	mmFBC_MISC, 0x00200000, 0x50100000,
71 	mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
72 	mmMC_ARB_WTM_CNTL_RD, 0x00000003, 0x000007ff,
73 	mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
74 	mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
75 	mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
76 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
77 	mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
78 	mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a,
79 	0x000c, 0xffffffff, 0x0040,
80 	0x000d, 0x00000040, 0x00004040,
81 	mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
82 	mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000,
83 	mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000,
84 	mmSX_DEBUG_1, 0x0000007f, 0x00000020,
85 	mmTA_CNTL_AUX, 0x00010000, 0x00010000,
86 	mmTCP_ADDR_CONFIG, 0x00000200, 0x000002fb,
87 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
88 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
89 	mmVGT_FIFO_DEPTHS, 0xffffffff, 0x000fff40,
90 	mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
91 	mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8,
92 	mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
93 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
94 	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
95 	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
96 	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
101 	mmMCIF_MEM_CONTROL, 0x00000001, 0x00000001,
106 	mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
107 	mmRLC_LB_PARAMS, 0xffffffff, 0x00601005,
108 	0x311f, 0xffffffff, 0x10104040,
109 	0x3122, 0xffffffff, 0x0100000a,
110 	mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
111 	mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
112 	mmUVD_CGC_GATE, 0x00000008, 0x00000000,
117 	mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
118 	mmCB_HW_CONTROL, 0x00010000, 0x00018208,
119 	mmDB_DEBUG, 0xffffffff, 0x00000000,
120 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
121 	mmDB_DEBUG3, 0x0002021c, 0x00020200,
122 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
123 	0x340c, 0x000300c0, 0x00800040,
124 	0x360c, 0x000300c0, 0x00800040,
125 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
126 	mmFBC_MISC, 0x00200000, 0x50100000,
127 	mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
128 	mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
129 	mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
130 	mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
131 	mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
132 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
133 	mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
134 	mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a,
135 	0x000c, 0xffffffff, 0x0040,
136 	0x000d, 0x00000040, 0x00004040,
137 	mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
138 	mmSX_DEBUG_1, 0x0000007f, 0x00000020,
139 	mmTA_CNTL_AUX, 0x00010000, 0x00010000,
140 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
141 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
142 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
143 	mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
144 	mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
145 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
146 	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
147 	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
148 	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
153 	mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
154 	mmRLC_LB_PARAMS, 0xffffffff, 0x00601004,
155 	0x311f, 0xffffffff, 0x10102020,
156 	0x3122, 0xffffffff, 0x01000020,
157 	mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
158 	mmRLC_LB_CNTL, 0xffffffff, 0x800000a4,
163 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x40000,
164 	mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x200010ff,
165 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
166 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
167 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
168 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
169 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
170 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x7007,
171 	mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x300010ff,
172 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
173 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
174 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
175 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
176 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
177 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x400000,
178 	mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x100010ff,
179 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
180 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
181 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
182 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
183 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
184 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x120200,
185 	mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x500010ff,
186 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
187 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
188 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
189 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
190 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
191 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x1e1e16,
192 	mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x600010ff,
193 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
194 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
195 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
196 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
197 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
198 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x171f1e,
199 	mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x700010ff,
200 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
201 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
202 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
203 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
204 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
205 	mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
206 	mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x9ff,
207 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x0,
208 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10000800,
209 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf,
210 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf,
211 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4,
212 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1000051e,
213 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff,
214 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff,
215 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x8,
216 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x80500,
217 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x12,
218 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x9050c,
219 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1d,
220 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xb052c,
221 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2a,
222 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1053e,
223 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2d,
224 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10546,
225 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x30,
226 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xa054e,
227 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3c,
228 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1055f,
229 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3f,
230 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10567,
231 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x42,
232 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1056f,
233 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x45,
234 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10572,
235 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x48,
236 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20575,
237 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4c,
238 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x190801,
239 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x67,
240 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1082a,
241 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x6a,
242 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1b082d,
243 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x87,
244 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x310851,
245 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xba,
246 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x891,
247 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbc,
248 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x893,
249 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbe,
250 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20895,
251 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc2,
252 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20899,
253 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc6,
254 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2089d,
255 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xca,
256 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a1,
257 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xcc,
258 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a3,
259 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xce,
260 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x308a5,
261 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xd3,
262 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x6d08cd,
263 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x142,
264 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2000095a,
265 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1,
266 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x144,
267 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x301f095b,
268 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x165,
269 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc094d,
270 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x173,
271 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf096d,
272 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x184,
273 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x15097f,
274 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x19b,
275 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc0998,
276 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1a9,
277 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x409a7,
278 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1af,
279 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xcdc,
280 	mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1b1,
281 	mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x800,
282 	mmGMCON_RENG_EXECUTE, 0xffffffff, 0x6c9b2000,
283 	mmGMCON_MISC2, 0xfc00, 0x2000,
284 	mmGMCON_MISC3, 0xffffffff, 0xfc0,
285 	mmMC_PMG_AUTO_CFG, 0x00000100, 0x100,
290 	mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002,
291 	mmRLC_LB_PARAMS, 0xffffffff, 0x033f1005,
292 	0x311f, 0xffffffff, 0x10808020,
293 	0x3122, 0xffffffff, 0x00800008,
294 	mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000,
295 	mmRLC_LB_CNTL, 0xffffffff, 0x80010014,
300 	mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
301 	mmCB_HW_CONTROL, 0x00010000, 0x00018208,
302 	mmDB_DEBUG, 0xffffffff, 0x00000000,
303 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
304 	mmDB_DEBUG3, 0x0002021c, 0x00020200,
305 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
306 	0x340c, 0x000300c0, 0x00800040,
307 	0x360c, 0x000300c0, 0x00800040,
308 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
309 	mmFBC_MISC, 0x00200000, 0x50100000,
310 	mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
311 	mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
312 	mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
313 	mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
314 	mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
315 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
316 	mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
317 	mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x0000124a,
318 	0x000c, 0xffffffff, 0x0040,
319 	0x000d, 0x00000040, 0x00004040,
320 	mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
321 	mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000,
322 	mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000,
323 	mmSX_DEBUG_1, 0x0000007f, 0x00000020,
324 	mmTA_CNTL_AUX, 0x00010000, 0x00010000,
325 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x00000003,
326 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
327 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001032,
328 	mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
329 	mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
330 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
331 	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
332 	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
333 	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
338 	mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
339 	mmCB_HW_CONTROL, 0x00010000, 0x00018208,
340 	mmDB_DEBUG, 0xffffffff, 0x00000000,
341 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
342 	mmDB_DEBUG3, 0x0002021c, 0x00020200,
343 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
344 	0x340c, 0x000300c0, 0x00800040,
345 	0x360c, 0x000300c0, 0x00800040,
346 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
347 	mmFBC_MISC, 0x00200000, 0x50100000,
348 	mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
349 	mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
350 	mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
351 	mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
352 	mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
353 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
354 	mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
355 	mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000082,
356 	0x000c, 0xffffffff, 0x0040,
357 	0x000d, 0x00000040, 0x00004040,
358 	mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
359 	mmSX_DEBUG_1, 0x0000007f, 0x00000020,
360 	mmTA_CNTL_AUX, 0x00010000, 0x00010000,
361 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
362 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
363 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
364 	mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
365 	mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
366 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
367 	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
368 	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
369 	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
375 	mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002,
376 	mmRLC_LB_PARAMS, 0xffffffff, 0x00601005,
377 	0x311f, 0xffffffff, 0x10104040,
378 	0x3122, 0xffffffff, 0x0100000a,
379 	mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
380 	mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
385 	0x17bc, 0x00000030, 0x00000011,
386 	mmCB_HW_CONTROL, 0x00010000, 0x00018208,
387 	mmDB_DEBUG, 0xffffffff, 0x00000000,
388 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
389 	mmDB_DEBUG3, 0x0002021c, 0x00020200,
390 	0x031e, 0x00000080, 0x00000000,
391 	0x3430, 0xff000fff, 0x00000100,
392 	0x340c, 0x000300c0, 0x00800040,
393 	0x3630, 0xff000fff, 0x00000100,
394 	0x360c, 0x000300c0, 0x00800040,
395 	0x16ec, 0x000000f0, 0x00000070,
396 	0x16f0, 0x00200000, 0x50100000,
397 	0x1c0c, 0x31000311, 0x00000011,
398 	mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
399 	mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
400 	mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
401 	mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
402 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
403 	mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
404 	mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000000,
405 	0x000c, 0xffffffff, 0x0040,
406 	0x000d, 0x00000040, 0x00004040,
407 	mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000,
408 	mmSX_DEBUG_1, 0x0000007f, 0x00000020,
409 	mmTA_CNTL_AUX, 0x00010000, 0x00010000,
410 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
411 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
412 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
413 	mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
414 	mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
415 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
416 	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
417 	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
418 	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
423 	mmGB_ADDR_CONFIG, 0xffffffff, 0x2011003,
428 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
429 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
430 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
431 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
432 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
433 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
434 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
435 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
436 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
437 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
438 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
439 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
440 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
441 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
442 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
443 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
444 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
445 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
446 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
447 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
448 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
449 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
450 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
451 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
452 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
453 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
454 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
455 	0x2458, 0xffffffff, 0x00010000,
456 	0x2459, 0xffffffff, 0x00030002,
457 	0x245a, 0xffffffff, 0x00040007,
458 	0x245b, 0xffffffff, 0x00060005,
459 	0x245c, 0xffffffff, 0x00090008,
460 	0x245d, 0xffffffff, 0x00020001,
461 	0x245e, 0xffffffff, 0x00040003,
462 	0x245f, 0xffffffff, 0x00000007,
463 	0x2460, 0xffffffff, 0x00060005,
464 	0x2461, 0xffffffff, 0x00090008,
465 	0x2462, 0xffffffff, 0x00030002,
466 	0x2463, 0xffffffff, 0x00050004,
467 	0x2464, 0xffffffff, 0x00000008,
468 	0x2465, 0xffffffff, 0x00070006,
469 	0x2466, 0xffffffff, 0x000a0009,
470 	0x2467, 0xffffffff, 0x00040003,
471 	0x2468, 0xffffffff, 0x00060005,
472 	0x2469, 0xffffffff, 0x00000009,
473 	0x246a, 0xffffffff, 0x00080007,
474 	0x246b, 0xffffffff, 0x000b000a,
475 	0x246c, 0xffffffff, 0x00050004,
476 	0x246d, 0xffffffff, 0x00070006,
477 	0x246e, 0xffffffff, 0x0008000b,
478 	0x246f, 0xffffffff, 0x000a0009,
479 	0x2470, 0xffffffff, 0x000d000c,
480 	0x2471, 0xffffffff, 0x00060005,
481 	0x2472, 0xffffffff, 0x00080007,
482 	0x2473, 0xffffffff, 0x0000000b,
483 	0x2474, 0xffffffff, 0x000a0009,
484 	0x2475, 0xffffffff, 0x000d000c,
485 	0x2476, 0xffffffff, 0x00070006,
486 	0x2477, 0xffffffff, 0x00090008,
487 	0x2478, 0xffffffff, 0x0000000c,
488 	0x2479, 0xffffffff, 0x000b000a,
489 	0x247a, 0xffffffff, 0x000e000d,
490 	0x247b, 0xffffffff, 0x00080007,
491 	0x247c, 0xffffffff, 0x000a0009,
492 	0x247d, 0xffffffff, 0x0000000d,
493 	0x247e, 0xffffffff, 0x000c000b,
494 	0x247f, 0xffffffff, 0x000f000e,
495 	0x2480, 0xffffffff, 0x00090008,
496 	0x2481, 0xffffffff, 0x000b000a,
497 	0x2482, 0xffffffff, 0x000c000f,
498 	0x2483, 0xffffffff, 0x000e000d,
499 	0x2484, 0xffffffff, 0x00110010,
500 	0x2485, 0xffffffff, 0x000a0009,
501 	0x2486, 0xffffffff, 0x000c000b,
502 	0x2487, 0xffffffff, 0x0000000f,
503 	0x2488, 0xffffffff, 0x000e000d,
504 	0x2489, 0xffffffff, 0x00110010,
505 	0x248a, 0xffffffff, 0x000b000a,
506 	0x248b, 0xffffffff, 0x000d000c,
507 	0x248c, 0xffffffff, 0x00000010,
508 	0x248d, 0xffffffff, 0x000f000e,
509 	0x248e, 0xffffffff, 0x00120011,
510 	0x248f, 0xffffffff, 0x000c000b,
511 	0x2490, 0xffffffff, 0x000e000d,
512 	0x2491, 0xffffffff, 0x00000011,
513 	0x2492, 0xffffffff, 0x0010000f,
514 	0x2493, 0xffffffff, 0x00130012,
515 	0x2494, 0xffffffff, 0x000d000c,
516 	0x2495, 0xffffffff, 0x000f000e,
517 	0x2496, 0xffffffff, 0x00100013,
518 	0x2497, 0xffffffff, 0x00120011,
519 	0x2498, 0xffffffff, 0x00150014,
520 	0x2499, 0xffffffff, 0x000e000d,
521 	0x249a, 0xffffffff, 0x0010000f,
522 	0x249b, 0xffffffff, 0x00000013,
523 	0x249c, 0xffffffff, 0x00120011,
524 	0x249d, 0xffffffff, 0x00150014,
525 	0x249e, 0xffffffff, 0x000f000e,
526 	0x249f, 0xffffffff, 0x00110010,
527 	0x24a0, 0xffffffff, 0x00000014,
528 	0x24a1, 0xffffffff, 0x00130012,
529 	0x24a2, 0xffffffff, 0x00160015,
530 	0x24a3, 0xffffffff, 0x0010000f,
531 	0x24a4, 0xffffffff, 0x00120011,
532 	0x24a5, 0xffffffff, 0x00000015,
533 	0x24a6, 0xffffffff, 0x00140013,
534 	0x24a7, 0xffffffff, 0x00170016,
535 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
536 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
537 	mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
538 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
539 	0x000c, 0xffffffff, 0x0000001c,
540 	0x000d, 0x000f0000, 0x000f0000,
541 	0x0583, 0xffffffff, 0x00000100,
542 	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
543 	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
544 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
545 	mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
546 	mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
547 	mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
548 	0x157a, 0x00000001, 0x00000001,
549 	mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
550 	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
551 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
552 	0x3430, 0xfffffff0, 0x00000100,
553 	0x3630, 0xfffffff0, 0x00000100,
557 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
558 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
559 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
560 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
561 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
562 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
563 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
564 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
565 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
566 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
567 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
568 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
569 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
570 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
571 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
572 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
573 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
574 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
575 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
576 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
577 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
578 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
579 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
580 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
581 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
582 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
583 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
584 	0x2458, 0xffffffff, 0x00010000,
585 	0x2459, 0xffffffff, 0x00030002,
586 	0x245a, 0xffffffff, 0x00040007,
587 	0x245b, 0xffffffff, 0x00060005,
588 	0x245c, 0xffffffff, 0x00090008,
589 	0x245d, 0xffffffff, 0x00020001,
590 	0x245e, 0xffffffff, 0x00040003,
591 	0x245f, 0xffffffff, 0x00000007,
592 	0x2460, 0xffffffff, 0x00060005,
593 	0x2461, 0xffffffff, 0x00090008,
594 	0x2462, 0xffffffff, 0x00030002,
595 	0x2463, 0xffffffff, 0x00050004,
596 	0x2464, 0xffffffff, 0x00000008,
597 	0x2465, 0xffffffff, 0x00070006,
598 	0x2466, 0xffffffff, 0x000a0009,
599 	0x2467, 0xffffffff, 0x00040003,
600 	0x2468, 0xffffffff, 0x00060005,
601 	0x2469, 0xffffffff, 0x00000009,
602 	0x246a, 0xffffffff, 0x00080007,
603 	0x246b, 0xffffffff, 0x000b000a,
604 	0x246c, 0xffffffff, 0x00050004,
605 	0x246d, 0xffffffff, 0x00070006,
606 	0x246e, 0xffffffff, 0x0008000b,
607 	0x246f, 0xffffffff, 0x000a0009,
608 	0x2470, 0xffffffff, 0x000d000c,
609 	0x2480, 0xffffffff, 0x00090008,
610 	0x2481, 0xffffffff, 0x000b000a,
611 	0x2482, 0xffffffff, 0x000c000f,
612 	0x2483, 0xffffffff, 0x000e000d,
613 	0x2484, 0xffffffff, 0x00110010,
614 	0x2485, 0xffffffff, 0x000a0009,
615 	0x2486, 0xffffffff, 0x000c000b,
616 	0x2487, 0xffffffff, 0x0000000f,
617 	0x2488, 0xffffffff, 0x000e000d,
618 	0x2489, 0xffffffff, 0x00110010,
619 	0x248a, 0xffffffff, 0x000b000a,
620 	0x248b, 0xffffffff, 0x000d000c,
621 	0x248c, 0xffffffff, 0x00000010,
622 	0x248d, 0xffffffff, 0x000f000e,
623 	0x248e, 0xffffffff, 0x00120011,
624 	0x248f, 0xffffffff, 0x000c000b,
625 	0x2490, 0xffffffff, 0x000e000d,
626 	0x2491, 0xffffffff, 0x00000011,
627 	0x2492, 0xffffffff, 0x0010000f,
628 	0x2493, 0xffffffff, 0x00130012,
629 	0x2494, 0xffffffff, 0x000d000c,
630 	0x2495, 0xffffffff, 0x000f000e,
631 	0x2496, 0xffffffff, 0x00100013,
632 	0x2497, 0xffffffff, 0x00120011,
633 	0x2498, 0xffffffff, 0x00150014,
634 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
635 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
636 	mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
637 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
638 	0x000c, 0xffffffff, 0x0000001c,
639 	0x000d, 0x000f0000, 0x000f0000,
640 	0x0583, 0xffffffff, 0x00000100,
641 	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
642 	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
643 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
644 	mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
645 	0x157a, 0x00000001, 0x00000001,
646 	mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
647 	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
648 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
649 	0x3430, 0xfffffff0, 0x00000100,
650 	0x3630, 0xfffffff0, 0x00000100,
655 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
656 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
657 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
658 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
659 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
660 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
661 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
662 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
663 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
664 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
665 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
666 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
667 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
668 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
669 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
670 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
671 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
672 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
673 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
674 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
675 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
676 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
677 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
678 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
679 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
680 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
681 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
682 	0x2458, 0xffffffff, 0x00010000,
683 	0x2459, 0xffffffff, 0x00030002,
684 	0x245a, 0xffffffff, 0x00040007,
685 	0x245b, 0xffffffff, 0x00060005,
686 	0x245c, 0xffffffff, 0x00090008,
687 	0x245d, 0xffffffff, 0x00020001,
688 	0x245e, 0xffffffff, 0x00040003,
689 	0x245f, 0xffffffff, 0x00000007,
690 	0x2460, 0xffffffff, 0x00060005,
691 	0x2461, 0xffffffff, 0x00090008,
692 	0x2462, 0xffffffff, 0x00030002,
693 	0x2463, 0xffffffff, 0x00050004,
694 	0x2464, 0xffffffff, 0x00000008,
695 	0x2465, 0xffffffff, 0x00070006,
696 	0x2466, 0xffffffff, 0x000a0009,
697 	0x2467, 0xffffffff, 0x00040003,
698 	0x2468, 0xffffffff, 0x00060005,
699 	0x2469, 0xffffffff, 0x00000009,
700 	0x246a, 0xffffffff, 0x00080007,
701 	0x246b, 0xffffffff, 0x000b000a,
702 	0x246c, 0xffffffff, 0x00050004,
703 	0x246d, 0xffffffff, 0x00070006,
704 	0x246e, 0xffffffff, 0x0008000b,
705 	0x246f, 0xffffffff, 0x000a0009,
706 	0x2470, 0xffffffff, 0x000d000c,
707 	0x2480, 0xffffffff, 0x00090008,
708 	0x2481, 0xffffffff, 0x000b000a,
709 	0x2482, 0xffffffff, 0x000c000f,
710 	0x2483, 0xffffffff, 0x000e000d,
711 	0x2484, 0xffffffff, 0x00110010,
712 	0x2485, 0xffffffff, 0x000a0009,
713 	0x2486, 0xffffffff, 0x000c000b,
714 	0x2487, 0xffffffff, 0x0000000f,
715 	0x2488, 0xffffffff, 0x000e000d,
716 	0x2489, 0xffffffff, 0x00110010,
717 	0x248a, 0xffffffff, 0x000b000a,
718 	0x248b, 0xffffffff, 0x000d000c,
719 	0x248c, 0xffffffff, 0x00000010,
720 	0x248d, 0xffffffff, 0x000f000e,
721 	0x248e, 0xffffffff, 0x00120011,
722 	0x248f, 0xffffffff, 0x000c000b,
723 	0x2490, 0xffffffff, 0x000e000d,
724 	0x2491, 0xffffffff, 0x00000011,
725 	0x2492, 0xffffffff, 0x0010000f,
726 	0x2493, 0xffffffff, 0x00130012,
727 	0x2494, 0xffffffff, 0x000d000c,
728 	0x2495, 0xffffffff, 0x000f000e,
729 	0x2496, 0xffffffff, 0x00100013,
730 	0x2497, 0xffffffff, 0x00120011,
731 	0x2498, 0xffffffff, 0x00150014,
732 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
733 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
734 	mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
735 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
736 	0x000c, 0xffffffff, 0x0000001c,
737 	0x000d, 0x000f0000, 0x000f0000,
738 	0x0583, 0xffffffff, 0x00000100,
739 	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
740 	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
741 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
742 	mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
743 	mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
744 	mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
745 	0x157a, 0x00000001, 0x00000001,
746 	mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
747 	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
748 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
749 	0x3430, 0xfffffff0, 0x00000100,
750 	0x3630, 0xfffffff0, 0x00000100,
755 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
756 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
757 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
758 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
759 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
760 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
761 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
762 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
763 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
764 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
765 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
766 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
767 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
768 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
769 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
770 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
771 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
772 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
773 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
774 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
775 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
776 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
777 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
778 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
779 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
780 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
781 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
782 	0x2458, 0xffffffff, 0x00010000,
783 	0x2459, 0xffffffff, 0x00030002,
784 	0x245a, 0xffffffff, 0x00040007,
785 	0x245b, 0xffffffff, 0x00060005,
786 	0x245c, 0xffffffff, 0x00090008,
787 	0x245d, 0xffffffff, 0x00020001,
788 	0x245e, 0xffffffff, 0x00040003,
789 	0x245f, 0xffffffff, 0x00000007,
790 	0x2460, 0xffffffff, 0x00060005,
791 	0x2461, 0xffffffff, 0x00090008,
792 	0x2462, 0xffffffff, 0x00030002,
793 	0x2463, 0xffffffff, 0x00050004,
794 	0x2464, 0xffffffff, 0x00000008,
795 	0x2465, 0xffffffff, 0x00070006,
796 	0x2466, 0xffffffff, 0x000a0009,
797 	0x2467, 0xffffffff, 0x00040003,
798 	0x2468, 0xffffffff, 0x00060005,
799 	0x2469, 0xffffffff, 0x00000009,
800 	0x246a, 0xffffffff, 0x00080007,
801 	0x246b, 0xffffffff, 0x000b000a,
802 	0x246c, 0xffffffff, 0x00050004,
803 	0x246d, 0xffffffff, 0x00070006,
804 	0x246e, 0xffffffff, 0x0008000b,
805 	0x246f, 0xffffffff, 0x000a0009,
806 	0x2470, 0xffffffff, 0x000d000c,
807 	0x2471, 0xffffffff, 0x00060005,
808 	0x2472, 0xffffffff, 0x00080007,
809 	0x2473, 0xffffffff, 0x0000000b,
810 	0x2474, 0xffffffff, 0x000a0009,
811 	0x2475, 0xffffffff, 0x000d000c,
812 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
813 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
814 	mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
815 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
816 	0x000c, 0xffffffff, 0x0000001c,
817 	0x000d, 0x000f0000, 0x000f0000,
818 	0x0583, 0xffffffff, 0x00000100,
819 	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
820 	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
821 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
822 	mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
823 	mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
824 	mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
825 	0x157a, 0x00000001, 0x00000001,
826 	mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
827 	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
828 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
829 	0x3430, 0xfffffff0, 0x00000100,
830 	0x3630, 0xfffffff0, 0x00000100,
835 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
836 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
837 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
838 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
839 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
840 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
841 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
842 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
843 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
844 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
845 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
846 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
847 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
848 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
849 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
850 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
851 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
852 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
853 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
854 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
855 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
856 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
857 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
858 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
859 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
860 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
861 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
862 	0x2458, 0xffffffff, 0x00010000,
863 	0x2459, 0xffffffff, 0x00030002,
864 	0x245a, 0xffffffff, 0x00040007,
865 	0x245b, 0xffffffff, 0x00060005,
866 	0x245c, 0xffffffff, 0x00090008,
867 	0x245d, 0xffffffff, 0x00020001,
868 	0x245e, 0xffffffff, 0x00040003,
869 	0x245f, 0xffffffff, 0x00000007,
870 	0x2460, 0xffffffff, 0x00060005,
871 	0x2461, 0xffffffff, 0x00090008,
872 	0x2462, 0xffffffff, 0x00030002,
873 	0x2463, 0xffffffff, 0x00050004,
874 	0x2464, 0xffffffff, 0x00000008,
875 	0x2465, 0xffffffff, 0x00070006,
876 	0x2466, 0xffffffff, 0x000a0009,
877 	0x2467, 0xffffffff, 0x00040003,
878 	0x2468, 0xffffffff, 0x00060005,
879 	0x2469, 0xffffffff, 0x00000009,
880 	0x246a, 0xffffffff, 0x00080007,
881 	0x246b, 0xffffffff, 0x000b000a,
882 	0x246c, 0xffffffff, 0x00050004,
883 	0x246d, 0xffffffff, 0x00070006,
884 	0x246e, 0xffffffff, 0x0008000b,
885 	0x246f, 0xffffffff, 0x000a0009,
886 	0x2470, 0xffffffff, 0x000d000c,
887 	0x2471, 0xffffffff, 0x00060005,
888 	0x2472, 0xffffffff, 0x00080007,
889 	0x2473, 0xffffffff, 0x0000000b,
890 	0x2474, 0xffffffff, 0x000a0009,
891 	0x2475, 0xffffffff, 0x000d000c,
892 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
893 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
894 	mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
895 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
896 	0x000c, 0xffffffff, 0x0000001c,
897 	0x000d, 0x000f0000, 0x000f0000,
898 	0x0583, 0xffffffff, 0x00000100,
899 	0x0409, 0xffffffff, 0x00000100,
900 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
901 	mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
902 	mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
903 	mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
904 	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
905 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
906 	0x3430, 0xfffffff0, 0x00000100,
907 	0x3630, 0xfffffff0, 0x00000100,
911 #if 0
920 		.max_level = 0,
932 	.codec_count = 0,
939 	.codec_count = 0,
985 	.codec_count = 0,
992 	switch (adev->asic_type) {  in si_query_video_codecs()
1000 		return 0;  in si_query_video_codecs()
1006 		return 0;  in si_query_video_codecs()
1012 		return 0;  in si_query_video_codecs()
1014 		return -EINVAL;  in si_query_video_codecs()
1023 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in si_pcie_rreg()
1027 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in si_pcie_rreg()
1035 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in si_pcie_wreg()
1040 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in si_pcie_wreg()
1048 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in si_pciep_rreg()
1049 	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));  in si_pciep_rreg()
1052 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in si_pciep_rreg()
1060 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in si_pciep_wreg()
1061 	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));  in si_pciep_wreg()
1065 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in si_pciep_wreg()
1073 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in si_smc_rreg()
1076 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in si_smc_rreg()
1084 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in si_smc_wreg()
1087 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in si_smc_wreg()
1095 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in si_uvd_ctx_rreg()
1096 	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));  in si_uvd_ctx_rreg()
1098 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in si_uvd_ctx_rreg()
1106 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in si_uvd_ctx_wreg()
1107 	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));  in si_uvd_ctx_wreg()
1109 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in si_uvd_ctx_wreg()
1170 		unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;  in si_get_register_value()
1171 		unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;  in si_get_register_value()
1175 			return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;  in si_get_register_value()
1177 			return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;  in si_get_register_value()
1179 			return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;  in si_get_register_value()
1182 		mutex_lock(&adev->grbm_idx_mutex);  in si_get_register_value()
1183 		if (se_num != 0xffffffff || sh_num != 0xffffffff)  in si_get_register_value()
1184 			amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);  in si_get_register_value()
1188 		if (se_num != 0xffffffff || sh_num != 0xffffffff)  in si_get_register_value()
1189 			amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in si_get_register_value()
1190 		mutex_unlock(&adev->grbm_idx_mutex);  in si_get_register_value()
1197 			return adev->gfx.config.gb_addr_config;  in si_get_register_value()
1199 			return adev->gfx.config.mc_arb_ramcfg;  in si_get_register_value()
1232 			idx = (reg_offset - mmGB_TILE_MODE0);  in si_get_register_value()
1233 			return adev->gfx.config.tile_mode_array[idx];  in si_get_register_value()
1244 	*value = 0;  in si_read_register()
1245 	for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {  in si_read_register()
1253 		return 0;  in si_read_register()
1255 	return -EINVAL;  in si_read_register()
1261 	u32 d1vga_control = 0;  in si_read_disabled_bios()
1262 	u32 d2vga_control = 0;  in si_read_disabled_bios()
1263 	u32 vga_render_control = 0;  in si_read_disabled_bios()
1268 	if (adev->mode_info.num_crtc) {  in si_read_disabled_bios()
1277 	if (adev->mode_info.num_crtc) {  in si_read_disabled_bios()
1294 	if (adev->mode_info.num_crtc) {  in si_read_disabled_bios()
1303 #define mmROM_INDEX 0x2A
1304 #define mmROM_DATA  0x2B
1314 	if (length_bytes == 0)  in si_read_bios_from_rom()
1317 	if (adev->flags & AMD_IS_APU)  in si_read_bios_from_rom()
1322 	/* set rom index to 0 */  in si_read_bios_from_rom()
1323 	WREG32(mmROM_INDEX, 0);  in si_read_bios_from_rom()
1324 	for (i = 0; i < length_dw; i++)  in si_read_bios_from_rom()
1342 	for (i = 0; i < adev->usec_timeout; i++) {  in si_set_clk_bypass_mode()
1381 	int r = -EINVAL;  in si_gpu_pci_config_reset()
1390 	pci_clear_master(adev->pdev);  in si_gpu_pci_config_reset()
1397 	for (i = 0; i < adev->usec_timeout; i++) {  in si_gpu_pci_config_reset()
1398 		if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {  in si_gpu_pci_config_reset()
1400 			pci_set_master(adev->pdev);  in si_gpu_pci_config_reset()
1401 			adev->has_hw_reset = true;  in si_gpu_pci_config_reset()
1402 			r = 0;  in si_gpu_pci_config_reset()
1414 	return 0;  in si_asic_supports_baco()
1423 		 amdgpu_reset_method != -1)  in si_asic_reset_method()
1424 		dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",  in si_asic_reset_method()
1436 		dev_info(adev->dev, "PCI reset\n");  in si_asic_reset()
1440 		dev_info(adev->dev, "PCI CONFIG reset\n");  in si_asic_reset()
1459 		temp &= ~(1<<0);  in si_vga_set_state()
1469 	u32 reference_clock = adev->clock.spll.reference_freq;  in si_get_xclk()
1485 	if (!ring || !ring->funcs->emit_wreg) {  in si_flush_hdp()
1496 	if (!ring || !ring->funcs->emit_wreg) {  in si_invalidate_hdp()
1519 	if (adev->flags & AMD_IS_APU)  in si_get_pcie_lanes()
1520 		return 0;  in si_get_pcie_lanes()
1544 	if (adev->flags & AMD_IS_APU)  in si_set_pcie_lanes()
1548 	case 0:  in si_set_pcie_lanes()
1583 	uint32_t perfctr = 0;  in si_get_pcie_usage()
1587 	/* This reports 0 on APUs, so return to avoid writing/reading registers  in si_get_pcie_usage()
1590 	if (adev->flags & AMD_IS_APU)  in si_get_pcie_usage()
1601 	 * Write 0x5:  in si_get_pcie_usage()
1602 	 * Bit 0 = Start all counters(1)  in si_get_pcie_usage()
1605 	WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);  in si_get_pcie_usage()
1610 	 * Write 0x2:  in si_get_pcie_usage()
1611 	 * Bit 0 = Stop counters(0)  in si_get_pcie_usage()
1614 	WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);  in si_get_pcie_usage()
1644 	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);  in si_uvd_send_upll_ctlreq()
1652 	for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) {  in si_uvd_send_upll_ctlreq()
1661 	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);  in si_uvd_send_upll_ctlreq()
1665 		return -ETIMEDOUT;  in si_uvd_send_upll_ctlreq()
1668 	return 0;  in si_uvd_send_upll_ctlreq()
1694  * si_calc_upll_dividers - calc UPLL clock dividers
1711  * Returns zero on success; -EINVAL on error.
1723 	unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq;  in si_calc_upll_dividers()
1726 	unsigned optimal_score = ~0;  in si_calc_upll_dividers()
1755 		score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);  in si_calc_upll_dividers()
1763 			if (optimal_score == 0)  in si_calc_upll_dividers()
1769 	if (optimal_score == ~0)  in si_calc_upll_dividers()
1770 		return -EINVAL;  in si_calc_upll_dividers()
1772 	return 0;  in si_calc_upll_dividers()
1777 	unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;  in si_set_uvd_clocks()
1790 		return 0;  in si_set_uvd_clocks()
1794 				  16384, 0x03FFFFFF, 0, 128, 5,  in si_set_uvd_clocks()
1799 	/* Set RESET_ANTI_MUX to 0 */  in si_set_uvd_clocks()
1800 	WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);  in si_set_uvd_clocks()
1806 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);  in si_set_uvd_clocks()
1809 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in si_set_uvd_clocks()
1821 	WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in si_set_uvd_clocks()
1826 	/* Set ref divider to 0 */  in si_set_uvd_clocks()
1827 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);  in si_set_uvd_clocks()
1830 		WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);  in si_set_uvd_clocks()
1845 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in si_set_uvd_clocks()
1850 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);  in si_set_uvd_clocks()
1863 	return 0;  in si_set_uvd_clocks()
1871 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
1879 	for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) {  in si_vce_send_vcepll_ctlreq()
1888 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
1892 		return -ETIMEDOUT;  in si_vce_send_vcepll_ctlreq()
1895 	return 0;  in si_vce_send_vcepll_ctlreq()
1900 	unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0;  in si_set_vce_clocks()
1916 		return 0;  in si_set_vce_clocks()
1920 				  16384, 0x03FFFFFF, 0, 128, 5,  in si_set_vce_clocks()
1925 	/* Set RESET_ANTI_MUX to 0 */  in si_set_vce_clocks()
1926 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);  in si_set_vce_clocks()
1932 	/* Toggle VCEPLL_SLEEP to 1 then back to 0 */  in si_set_vce_clocks()
1935 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);  in si_set_vce_clocks()
1938 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
1950 	WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in si_set_vce_clocks()
1957 	/* Set ref divider to 0 */  in si_set_vce_clocks()
1958 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);  in si_set_vce_clocks()
1969 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
1974 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);  in si_set_vce_clocks()
1987 	return 0;  in si_set_vce_clocks()
2029 	adev->smc_rreg = &si_smc_rreg;  in si_common_early_init()
2030 	adev->smc_wreg = &si_smc_wreg;  in si_common_early_init()
2031 	adev->pcie_rreg = &si_pcie_rreg;  in si_common_early_init()
2032 	adev->pcie_wreg = &si_pcie_wreg;  in si_common_early_init()
2033 	adev->pciep_rreg = &si_pciep_rreg;  in si_common_early_init()
2034 	adev->pciep_wreg = &si_pciep_wreg;  in si_common_early_init()
2035 	adev->uvd_ctx_rreg = si_uvd_ctx_rreg;  in si_common_early_init()
2036 	adev->uvd_ctx_wreg = si_uvd_ctx_wreg;  in si_common_early_init()
2037 	adev->didt_rreg = NULL;  in si_common_early_init()
2038 	adev->didt_wreg = NULL;  in si_common_early_init()
2040 	adev->asic_funcs = &si_asic_funcs;  in si_common_early_init()
2042 	adev->rev_id = si_get_rev_id(adev);  in si_common_early_init()
2043 	adev->external_rev_id = 0xFF;  in si_common_early_init()
2044 	switch (adev->asic_type) {  in si_common_early_init()
2046 		adev->cg_flags =  in si_common_early_init()
2060 		adev->pg_flags = 0;  in si_common_early_init()
2061 		adev->external_rev_id = (adev->rev_id == 0) ? 1 :  in si_common_early_init()
2062 					(adev->rev_id == 1) ? 5 : 6;  in si_common_early_init()
2065 		adev->cg_flags =  in si_common_early_init()
2081 		adev->pg_flags = 0;  in si_common_early_init()
2082 		adev->external_rev_id = adev->rev_id + 20;  in si_common_early_init()
2086 		adev->cg_flags =  in si_common_early_init()
2102 		adev->pg_flags = 0;  in si_common_early_init()
2104 		adev->external_rev_id = adev->rev_id + 40;  in si_common_early_init()
2107 		adev->cg_flags =  in si_common_early_init()
2122 		adev->pg_flags = 0;  in si_common_early_init()
2123 		adev->external_rev_id = 60;  in si_common_early_init()
2126 		adev->cg_flags =  in si_common_early_init()
2140 		adev->pg_flags = 0;  in si_common_early_init()
2141 		adev->external_rev_id = 70;  in si_common_early_init()
2145 		return -EINVAL;  in si_common_early_init()
2148 	return 0;  in si_common_early_init()
2153 	return 0;  in si_common_sw_init()
2158 	return 0;  in si_common_sw_fini()
2164 	switch (adev->asic_type) {  in si_init_golden_registers()
2235 	struct pci_dev *root = adev->pdev->bus->self;  in si_pcie_gen3_enable()
2240 	if (pci_is_root_bus(adev->pdev->bus))  in si_pcie_gen3_enable()
2243 	if (amdgpu_pcie_gen2 == 0)  in si_pcie_gen3_enable()
2246 	if (adev->flags & AMD_IS_APU)  in si_pcie_gen3_enable()
2249 	if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |  in si_pcie_gen3_enable()
2256 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {  in si_pcie_gen3_enable()
2261 		DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");  in si_pcie_gen3_enable()
2262 	} else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {  in si_pcie_gen3_enable()
2267 		DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");  in si_pcie_gen3_enable()
2270 	if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))  in si_pcie_gen3_enable()
2273 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {  in si_pcie_gen3_enable()
2280 			pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);  in si_pcie_gen3_enable()
2296 			for (i = 0; i < 10; i++) {  in si_pcie_gen3_enable()
2297 				pcie_capability_read_word(adev->pdev,  in si_pcie_gen3_enable()
2305 				pcie_capability_read_word(adev->pdev,  in si_pcie_gen3_enable()
2311 				pcie_capability_read_word(adev->pdev,  in si_pcie_gen3_enable()
2329 				pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,  in si_pcie_gen3_enable()
2340 				pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,  in si_pcie_gen3_enable()
2358 	tmp16 = 0;  in si_pcie_gen3_enable()
2359 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)  in si_pcie_gen3_enable()
2361 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)  in si_pcie_gen3_enable()
2365 	pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,  in si_pcie_gen3_enable()
2372 	for (i = 0; i < adev->usec_timeout; i++) {  in si_pcie_gen3_enable()
2374 		if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)  in si_pcie_gen3_enable()
2385 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in si_pif_phy0_rreg()
2386 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));  in si_pif_phy0_rreg()
2388 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in si_pif_phy0_rreg()
2396 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in si_pif_phy0_wreg()
2397 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));  in si_pif_phy0_wreg()
2399 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in si_pif_phy0_wreg()
2407 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in si_pif_phy1_rreg()
2408 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));  in si_pif_phy1_rreg()
2410 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in si_pif_phy1_rreg()
2418 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in si_pif_phy1_wreg()
2419 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));  in si_pif_phy1_wreg()
2421 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in si_pif_phy1_wreg()
2434 	data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;  in si_program_aspm()
2487 			if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) {  in si_program_aspm()
2536 			if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))  in si_program_aspm()
2543 			if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))  in si_program_aspm()
2549 			    !pci_is_root_bus(adev->pdev->bus)) {  in si_program_aspm()
2550 				struct pci_dev *root = adev->pdev->bus->self;  in si_program_aspm()
2630 	readrq = pcie_get_readrq(adev->pdev);  in si_fix_pci_max_read_req_size()
2631 	v = ffs(readrq) - 8;  in si_fix_pci_max_read_req_size()
2632 	if ((v == 0) || (v == 6) || (v == 7))  in si_fix_pci_max_read_req_size()
2633 		pcie_set_readrq(adev->pdev, 512);  in si_fix_pci_max_read_req_size()
2645 	return 0;  in si_common_hw_init()
2650 	return 0;  in si_common_hw_fini()
2674 	return 0;  in si_common_wait_for_idle()
2679 	return 0;  in si_common_soft_reset()
2685 	return 0;  in si_common_set_clockgating_state()
2691 	return 0;  in si_common_set_powergating_state()
2717 	.minor = 0,
2718 	.rev = 0,
2724 	switch (adev->asic_type) {  in si_set_ip_blocks()
2734 		if (adev->enable_virtual_display)  in si_set_ip_blocks()
2752 		if (adev->enable_virtual_display)  in si_set_ip_blocks()
2770 		if (adev->enable_virtual_display)  in si_set_ip_blocks()
2776 	return 0;  in si_set_ip_blocks()