Lines Matching +full:3 +full:- +full:31
33 #define PACKET_TYPE3 3
35 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
54 /* Packet 3 types */
58 #define CE_PARTITION_BASE 3
80 #define PACKET3_ATOMIC_MEM__COMMAND__SEND_AND_CONTINUE 3
84 #define PACKET3_ATOMIC_MEM__CACHE_POLICY__BYPASS 3
108 /* 0 - register
109 * 1 - memory (sync - via GRBM)
110 * 2 - gl2
111 * 3 - gds
112 * 4 - reserved
113 * 5 - memory (async - direct)
118 /* 0 - LRU
119 * 1 - Stream
122 /* 0 - me
123 * 1 - pfp
124 * 2 - ce
141 #define PACKET3_WRITE_DATA__DST_SEL__GDS 3
153 #define PACKET3_WRITE_DATA__TEMPORAL__LU 3
157 #define PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS 3
168 /* 0 - always
169 * 1 - <
170 * 2 - <=
171 * 3 - ==
172 * 4 - !=
173 * 5 - >=
174 * 6 - >
177 /* 0 - reg
178 * 1 - mem
181 /* 0 - wait_reg_mem
182 * 1 - wr_wait_wr_reg
185 /* 0 - me
186 * 1 - pfp
203 #define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31)
207 #define PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3
215 #define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3
219 #define PACKET3_WAIT_REG_MEM__CACHE_POLICY__BYPASS 3
223 #define PACKET3_WAIT_REG_MEM__TEMPORAL__LU 3
227 /* 0 - LRU
228 * 1 - Stream
229 * 2 - Bypass
242 #define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31)
246 #define PACKET3_INDIRECT_BUFFER__TEMPORAL__LU 3
250 #define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__BYPASS 3
263 #define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
270 #define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
283 #define PACKET3_COPY_DATA__SRC_SEL__GDS 3
293 #define PACKET3_COPY_DATA__DST_SEL__GDS 3
300 #define PACKET3_COPY_DATA__SRC_TEMPORAL__LU 3
304 #define PACKET3_COPY_DATA__SRC_CACHE_POLICY__BYPASS 3
314 #define PACKET3_COPY_DATA__DST_TEMPORAL__LU 3
318 #define PACKET3_COPY_DATA__DST_CACHE_POLICY__BYPASS 3
329 /* 0 - any non-TS event
330 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
331 * 2 - SAMPLE_PIPELINESTAT
332 * 3 - SAMPLE_STREAMOUTSTAT*
333 * 4 - *S_PARTIAL_FLUSH
339 #define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
351 #define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE3 3
368 /* 0 - cache_policy__me_release_mem__lru
369 * 1 - cache_policy__me_release_mem__stream
370 * 2 - cache_policy__me_release_mem__noa
371 * 3 - cache_policy__me_release_mem__bypass
376 /* 0 - discard
377 * 1 - send low 32bit data
378 * 2 - send 64bit data
379 * 3 - send 64bit GPU counter value
380 * 4 - send 64bit sys counter value
383 /* 0 - none
384 * 1 - interrupt only (DATA_SEL = 0)
385 * 2 - interrupt when data write is confirmed
388 /* 0 - MC
389 * 1 - TC/L2
396 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
400 * 3. SRC_ADDR_LO or DATA [31:0]
401 * 4. SRC_ADDR_HI [31:0]
402 * 5. DST_ADDR_LO [31:0]
404 * 7. COMMAND [31:26] | BYTE_COUNT [25:0]
408 /* 0 - ME
409 * 1 - PFP
412 /* 0 - LRU
413 * 1 - Stream
416 /* 0 - DST_ADDR using DAS
417 * 1 - GDS
418 * 3 - DST_ADDR using L2
421 /* 0 - LRU
422 * 1 - Stream
425 /* 0 - SRC_ADDR using SAS
426 * 1 - GDS
427 * 2 - DATA
428 * 3 - SRC_ADDR using L2
430 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
433 /* 0 - memory
434 * 1 - register
437 /* 0 - memory
438 * 1 - register
450 * 2.1 ENGINE_SEL [31:31]
451 * 2. COHER_SIZE [31:0]
452 * 3. COHER_SIZE_HI [7:0]
453 * 4. COHER_BASE_LO [31:0]
463 * 3:FIRST_LAST
470 * 3:FIRST_LAST
484 * 3:FIRST_LAST
584 * 3. QUEUE_MASK_LO [31:0]
585 * 4. QUEUE_MASK_HI [31:0]
586 * 5. GWS_MASK_LO [31:0]
587 * 6. GWS_MASK_HI [31:0]
598 * 3. CONTROL2
599 * 4. MQD_ADDR_LO [31:0]
600 * 5. MQD_ADDR_HI [31:0]
601 * 6. WPTR_ADDR_LO [31:0]
602 * 7. WPTR_ADDR_HI [31:0]
620 * 3. CONTROL2
627 /* 0 - PREEMPT_QUEUES
628 * 1 - RESET_QUEUES
629 * 2 - DISABLE_PROCESS_QUEUES
630 * 3 - PREEMPT_QUEUES_NO_UNMAP
650 * 3. CONTROL2
651 * 4. ADDR_LO [31:0]
652 * 5. ADDR_HI [31:0]
653 * 6. DATA_LO [31:0]
654 * 7. DATA_HI [31:0]
670 * 2. RESERVED [31:0]