31 #define	PACKET_TYPE1	1
52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
57 #define		PACKET3_BASE_INDEX(x)                  ((x) << 0)  argument
89 #define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)  argument
91 		 * 1 - memory (sync - via GRBM)
97 #define		WR_ONE_ADDR                             (1 << 16)
98 #define		WR_CONFIRM                              (1 << 20)
99 #define		WRITE_DATA_CACHE_POLICY(x)              ((x) << 25)  argument
101 		 * 1 - Stream
103 #define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)  argument
105 		 * 1 - pfp
111 #              define PACKET3_SEM_SEL_SIGNAL_TYPE   (0x1 << 20) /* 0 = increment, 1 = write 1 */
117 #define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)  argument
119 		 * 1 - <
126 #define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)  argument
128 		 * 1 - mem
130 #define		WAIT_REG_MEM_OPERATION(x)               ((x) << 6)  argument
132 		 * 1 - wr_wait_wr_reg
134 #define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)  argument
136 		 * 1 - pfp
139 #define		INDIRECT_BUFFER_VALID                   (1 << 23)
140 #define		INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) << 28)  argument
142 		 * 1 - Stream
145 #define		INDIRECT_BUFFER_PRE_ENB(x)		((x) << 21)  argument
146 #define		INDIRECT_BUFFER_PRE_RESUME(x)           ((x) << 30)  argument
155 #define		EVENT_TYPE(x)                           ((x) << 0)  argument
156 #define		EVENT_INDEX(x)                          ((x) << 8)  argument
158 		 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
166 #define		PACKET3_RELEASE_MEM_EVENT_TYPE(x)	((x) << 0)  argument
167 #define		PACKET3_RELEASE_MEM_EVENT_INDEX(x)	((x) << 8)  argument
168 #define		PACKET3_RELEASE_MEM_GCR_GLM_WB		(1 << 12)
169 #define		PACKET3_RELEASE_MEM_GCR_GLM_INV		(1 << 13)
170 #define		PACKET3_RELEASE_MEM_GCR_GLV_INV		(1 << 14)
171 #define		PACKET3_RELEASE_MEM_GCR_GL1_INV		(1 << 15)
172 #define		PACKET3_RELEASE_MEM_GCR_GL2_US		(1 << 16)
173 #define		PACKET3_RELEASE_MEM_GCR_GL2_RANGE	(1 << 17)
174 #define		PACKET3_RELEASE_MEM_GCR_GL2_DISCARD	(1 << 19)
175 #define		PACKET3_RELEASE_MEM_GCR_GL2_INV		(1 << 20)
176 #define		PACKET3_RELEASE_MEM_GCR_GL2_WB		(1 << 21)
177 #define		PACKET3_RELEASE_MEM_GCR_SEQ		(1 << 22)
178 #define		PACKET3_RELEASE_MEM_CACHE_POLICY(x)	((x) << 25)  argument
180 		 * 1 - cache_policy__me_release_mem__stream
184 #define		PACKET3_RELEASE_MEM_EXECUTE		(1 << 28)
186 #define		PACKET3_RELEASE_MEM_DATA_SEL(x)		((x) << 29)  argument
188 		 * 1 - send low 32bit data
193 #define		PACKET3_RELEASE_MEM_INT_SEL(x)		((x) << 24)  argument
195 		 * 1 - interrupt only (DATA_SEL = 0)
198 #define		PACKET3_RELEASE_MEM_DST_SEL(x)		((x) << 16)  argument
200 		 * 1 - TC/L2
209 /* 1. header
218 #              define PACKET3_DMA_DATA_ENGINE(x)     ((x) << 0)  argument
220 		 * 1 - PFP
222 #              define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)  argument
224 		 * 1 - Stream
226 #              define PACKET3_DMA_DATA_DST_SEL(x)  ((x) << 20)  argument
228 		 * 1 - GDS
231 #              define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)  argument
233 		 * 1 - Stream
235 #              define PACKET3_DMA_DATA_SRC_SEL(x)  ((x) << 29)  argument
237 		 * 1 - GDS
241 #              define PACKET3_DMA_DATA_CP_SYNC     (1 << 31)
243 #              define PACKET3_DMA_DATA_CMD_SAS     (1 << 26)
245 		 * 1 - register
247 #              define PACKET3_DMA_DATA_CMD_DAS     (1 << 27)
249 		 * 1 - register
251 #              define PACKET3_DMA_DATA_CMD_SAIC    (1 << 28)
252 #              define PACKET3_DMA_DATA_CMD_DAIC    (1 << 29)
253 #              define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
259 /* 1.  HEADER
269 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0)  argument
272 		 * 1:ALL
276 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2)  argument
279 		 * 1:reserved
283 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4)  argument
284 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5)  argument
285 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6)  argument
286 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7)  argument
287 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8)  argument
288 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9)  argument
289 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10)  argument
290 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11)  argument
293 		 * 1:VOL
297 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x)  ((x) << 13)  argument
298 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14)  argument
299 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15)  argument
300 #define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16)  argument
303 		 * 1: FORWARD
306 #define 	PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA  (1 << 18)
357 #			define FRAME_TMZ	(1 << 0)
358 #			define FRAME_CMD(x) ((x) << 28)  argument
360 			 * x=0: tmz_begin
361 			 * x=1: tmz_end
369 #              define PACKET3_INVALIDATE_TLBS_DST_SEL(x)     ((x) << 0)  argument
370 #              define PACKET3_INVALIDATE_TLBS_ALL_HUB(x)     ((x) << 4)  argument
371 #              define PACKET3_INVALIDATE_TLBS_PASID(x)       ((x) << 5)  argument
380 /* 1. header
389 #              define PACKET3_SET_RESOURCES_VMID_MASK(x)     ((x) << 0)  argument
390 #              define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)  argument
391 #              define PACKET3_SET_RESOURCES_QUEUE_TYPE(x)    ((x) << 29)  argument
394 /* 1. header
403 #              define PACKET3_MAP_QUEUES_QUEUE_SEL(x)       ((x) << 4)  argument
404 #              define PACKET3_MAP_QUEUES_VMID(x)            ((x) << 8)  argument
405 #              define PACKET3_MAP_QUEUES_QUEUE(x)           ((x) << 13)  argument
406 #              define PACKET3_MAP_QUEUES_PIPE(x)            ((x) << 16)  argument
407 #              define PACKET3_MAP_QUEUES_ME(x)              ((x) << 18)  argument
408 #              define PACKET3_MAP_QUEUES_QUEUE_TYPE(x)      ((x) << 21)  argument
409 #              define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x)    ((x) << 24)  argument
410 #              define PACKET3_MAP_QUEUES_ENGINE_SEL(x)      ((x) << 26)  argument
411 #              define PACKET3_MAP_QUEUES_NUM_QUEUES(x)      ((x) << 29)  argument
413 #              define PACKET3_MAP_QUEUES_CHECK_DISABLE(x)   ((x) << 1)  argument
414 #              define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)  argument
416 /* 1. header
424 #              define PACKET3_UNMAP_QUEUES_ACTION(x)           ((x) << 0)  argument
426 		 * 1 - RESET_QUEUES
430 #              define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x)        ((x) << 4)  argument
431 #              define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x)       ((x) << 26)  argument
432 #              define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x)       ((x) << 29)  argument
434 #              define PACKET3_UNMAP_QUEUES_PASID(x)            ((x) << 0)  argument
436 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)  argument
438 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)  argument
440 #              define PACKET3_UNMAP_QUEUES_RB_WPTR(x)          ((x) << 0)  argument
442 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)  argument
444 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)  argument
446 /* 1. header
455 #              define PACKET3_QUERY_STATUS_CONTEXT_ID(x)       ((x) << 0)  argument
456 #              define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x)    ((x) << 28)  argument
457 #              define PACKET3_QUERY_STATUS_COMMAND(x)          ((x) << 30)  argument
459 #              define PACKET3_QUERY_STATUS_PASID(x)            ((x) << 0)  argument
461 #              define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x)  ((x) << 2)  argument
462 #              define PACKET3_QUERY_STATUS_ENG_SEL(x)          ((x) << 25)  argument
467 #              define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x)  ((x) << 0)  argument
468 #              define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM    (1 << 0)