Lines Matching refs:ih_regs
51 struct amdgpu_ih_regs *ih_regs;
54 ih_regs = &adev->irq.ih.ih_regs;
55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
67 ih_regs = &adev->irq.ih1.ih_regs;
68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
78 ih_regs = &adev->irq.ih2.ih_regs;
79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
156 struct amdgpu_ih_regs *ih_regs;
159 ih_regs = &ih->ih_regs;
161 tmp = RREG32(ih_regs->ih_rb_cntl);
169 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
172 WREG32(ih_regs->ih_rb_cntl, tmp);
179 WREG32(ih_regs->ih_rb_rptr, 0);
180 WREG32(ih_regs->ih_rb_wptr, 0);
266 struct amdgpu_ih_regs *ih_regs;
269 ih_regs = &ih->ih_regs;
272 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
273 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
275 tmp = RREG32(ih_regs->ih_rb_cntl);
283 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
288 WREG32(ih_regs->ih_rb_cntl, tmp);
293 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
294 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
298 WREG32(ih_regs->ih_rb_wptr, 0);
299 WREG32(ih_regs->ih_rb_rptr, 0);
301 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih));
410 struct amdgpu_ih_regs *ih_regs;
424 ih_regs = &ih->ih_regs;
427 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
441 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
443 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
449 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
466 struct amdgpu_ih_regs *ih_regs;
468 ih_regs = &ih->ih_regs;
472 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
491 struct amdgpu_ih_regs *ih_regs;
504 ih_regs = &ih->ih_regs;
505 WREG32(ih_regs->ih_rb_rptr, ih->rptr);