Lines Matching refs:tmp
132 uint32_t tmp, inst_mask;
186 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2);
187 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
189 WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
195 uint32_t tmp, inst_mask;
199 tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
201 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
203 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
205 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
207 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
209 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
211 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
213 psp_reg_program_no_ring(&adev->psp, tmp, PSP_REG_MMHUB_L1_TLB_CNTL);
217 tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);
219 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
221 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
223 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
225 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
227 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
229 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
231 WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);
239 uint32_t tmp, inst_mask;
250 tmp = RREG32_SOC15_OFFSET(MMHUB, i,
252 tmp |= (1 << 15); /* SDMA client is BIT15 */
254 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, j * distance, tmp);
256 tmp = RREG32_SOC15_OFFSET(MMHUB, i,
258 tmp |= (1 << 15);
260 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, j * distance, tmp);
267 uint32_t tmp, inst_mask;
276 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL);
277 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
278 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
281 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
283 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION,
285 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
287 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
289 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL, tmp);
291 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL2);
292 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS,
294 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
295 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL2, tmp);
297 tmp = regVM_L2_CNTL3_DEFAULT;
299 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
300 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
303 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
304 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
307 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL3, tmp);
309 tmp = regVM_L2_CNTL4_DEFAULT;
312 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
314 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
317 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
319 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
322 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL4, tmp);
328 uint32_t tmp, inst_mask;
333 tmp = RREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL);
334 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
335 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
337 tmp = REG_SET_FIELD(tmp,
340 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
342 WREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL, tmp);
381 uint32_t tmp, inst_mask;
395 tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
397 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
399 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
401 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
403 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
405 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
407 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
409 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
411 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
413 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
415 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
422 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
425 i * hub->ctx_distance, tmp);
482 u32 tmp;
486 tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
487 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
488 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
490 psp_reg_program_no_ring(&adev->psp, tmp, PSP_REG_MMHUB_L1_TLB_CNTL);
494 tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);
495 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
497 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
499 WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);
507 u32 tmp;
519 tmp = RREG32_SOC15(MMHUB, j, regVM_L2_CNTL);
520 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE,
522 WREG32_SOC15(MMHUB, j, regVM_L2_CNTL, tmp);
538 u32 tmp, inst_mask;
546 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL);
547 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
549 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
551 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
553 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
555 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
558 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
560 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
562 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
564 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
566 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
568 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
571 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
573 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
577 WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp);