Lines Matching refs:mes
152 static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
158 struct amdgpu_device *adev = mes->adev;
159 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)];
160 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)];
286 static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes,
293 if (mes->enable_coop_mode)
294 xcc_id = mes->master_xcc_ids[inst];
341 return mes_v12_1_submit_pkt_and_poll_completion(mes,
347 static int mes_v12_1_remove_hw_queue(struct amdgpu_mes *mes,
354 if (mes->enable_coop_mode)
355 xcc_id = mes->master_xcc_ids[inst];
366 return mes_v12_1_submit_pkt_and_poll_completion(mes,
372 static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes,
388 if (mes->adev->enable_uni_mes)
393 return mes_v12_1_submit_pkt_and_poll_completion(mes,
399 static int mes_v12_1_map_legacy_queue(struct amdgpu_mes *mes,
420 if (mes->adev->enable_uni_mes)
425 return mes_v12_1_submit_pkt_and_poll_completion(mes,
431 static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes,
460 if (mes->adev->enable_uni_mes)
465 return mes_v12_1_submit_pkt_and_poll_completion(mes,
471 static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes,
489 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE,
494 static int mes_v12_1_resume_gang(struct amdgpu_mes *mes,
509 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE,
514 static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes,
525 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
553 static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
556 struct amdgpu_device *adev = mes->adev;
560 if (mes->adev->enable_uni_mes)
639 return mes_v12_1_submit_pkt_and_poll_completion(mes,
645 static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes,
660 if (mes->enable_coop_mode &&
662 ((mes->kiq_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) {
663 master_xcc_id = mes->master_xcc_ids[inst];
666 mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe];
669 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
674 static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes,
678 struct amdgpu_device *adev = mes->adev;
688 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
689 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
695 mes->compute_hqd_mask[i];
699 mes->gfx_hqd_mask[i];
703 mes->sdma_hqd_mask[i];
707 mes->aggregated_doorbells[i];
711 mes->sch_ctx_gpu_addr[pipe];
713 mes->query_status_fence_gpu_addr[pipe];
741 mes->event_log_gpu_addr + MES_PIPE_INST(xcc_id, pipe) * AMDGPU_MES_LOG_BUFFER_SIZE;
747 status = mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
756 adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);
758 adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);
766 static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes,
769 struct amdgpu_device *adev = mes->adev;
776 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
785 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
794 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
803 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
812 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
823 struct amdgpu_mes *mes, bool enable, int xcc_id)
825 struct amdgpu_device *adev = mes->adev;
843 static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes,
871 if (mes->adev->enable_uni_mes)
876 return mes_v12_1_submit_pkt_and_poll_completion(mes,
883 static int mes_v12_1_detect_and_reset_hung_queues(struct amdgpu_mes *mes,
897 mes->hung_queue_db_array_gpu_addr[0];
904 return mes_v12_1_submit_pkt_and_poll_completion(mes,
926 static int mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes *mes,
934 if (mes->enable_coop_mode)
935 xcc_id = mes->master_xcc_ids[inst];
947 /*convert amdgpu_mes_hub_id to mes expected hub_id */
952 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, AMDGPU_MES_KIQ_PIPE,
981 adev->mes.fw[pipe]->data;
983 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
990 &adev->mes.ucode_fw_obj[inst],
991 &adev->mes.ucode_fw_gpu_addr[inst],
992 (void **)&adev->mes.ucode_fw_ptr[inst]);
994 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
998 memcpy(adev->mes.ucode_fw_ptr[inst], fw_data, fw_size);
1000 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[inst]);
1001 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[inst]);
1016 adev->mes.fw[pipe]->data;
1018 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1025 &adev->mes.data_fw_obj[inst],
1026 &adev->mes.data_fw_gpu_addr[inst],
1027 (void **)&adev->mes.data_fw_ptr[inst]);
1029 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
1033 memcpy(adev->mes.data_fw_ptr[inst], fw_data, fw_size);
1035 amdgpu_bo_kunmap(adev->mes.data_fw_obj[inst]);
1036 amdgpu_bo_unreserve(adev->mes.data_fw_obj[inst]);
1047 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[inst],
1048 &adev->mes.data_fw_gpu_addr[inst],
1049 (void **)&adev->mes.data_fw_ptr[inst]);
1051 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[inst],
1052 &adev->mes.ucode_fw_gpu_addr[inst],
1053 (void **)&adev->mes.ucode_fw_ptr[inst]);
1073 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
1122 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
1143 if (!adev->mes.fw[pipe])
1164 lower_32_bits(adev->mes.ucode_fw_gpu_addr[inst]));
1166 upper_32_bits(adev->mes.ucode_fw_gpu_addr[inst]));
1173 lower_32_bits(adev->mes.data_fw_gpu_addr[inst]));
1175 upper_32_bits(adev->mes.data_fw_gpu_addr[inst]));
1208 &adev->mes.eop_gpu_obj[inst],
1209 &adev->mes.eop_gpu_addr[inst],
1217 adev->mes.eop_gpu_obj[inst]->tbo.base.size);
1219 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[inst]);
1220 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[inst]);
1233 &adev->mes.shared_cmd_buf_obj[inst],
1234 &adev->mes.shared_cmd_buf_gpu_addr[inst],
1432 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]);
1452 ring = &adev->mes.ring[MES_PIPE_INST(xcc_id, pipe)];
1485 ring = &adev->mes.ring[inst];
1497 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst];
1536 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst];
1562 ring = &adev->mes.ring[inst];
1578 adev->mes.mqd_backup[inst] = kmalloc(mqd_size, GFP_KERNEL);
1579 if (!adev->mes.mqd_backup[inst])
1592 adev->mes.funcs = &mes_v12_1_funcs;
1593 adev->mes.kiq_hw_init = &mes_v12_1_kiq_hw_init;
1594 adev->mes.kiq_hw_fini = &mes_v12_1_kiq_hw_fini;
1595 adev->mes.enable_legacy_queue_map = true;
1597 adev->mes.event_log_size =
1643 amdgpu_bo_free_kernel(&adev->mes.shared_cmd_buf_obj[inst],
1644 &adev->mes.shared_cmd_buf_gpu_addr[inst],
1647 kfree(adev->mes.mqd_backup[inst]);
1649 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst],
1650 &adev->mes.eop_gpu_addr[inst],
1654 amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj,
1655 &adev->mes.ring[inst].mqd_gpu_addr,
1656 &adev->mes.ring[inst].mqd_ptr);
1657 amdgpu_ring_fini(&adev->mes.ring[inst]);
1663 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1720 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = false;
1744 mes_v12_1_kiq_setting(&adev->mes.ring[inst], xcc_id);
1786 r = mes_v12_1_set_hw_resources(&adev->mes,
1791 mes_v12_1_set_hw_resources_1(&adev->mes,
1795 if (adev->mes.enable_legacy_queue_map) {
1812 if (adev->mes.ring[inst].sched.ready) {
1815 &adev->mes.ring[inst],
1820 adev->mes.ring[inst].sched.ready = false;
1844 adev->mes.enable_coop_mode = 1;
1845 adev->mes.master_xcc_ids[xcc_id] = 0;
1848 adev->mes.enable_coop_mode = 1;
1849 adev->mes.master_xcc_ids[xcc_id] =
1853 adev->mes.enable_coop_mode = 1;
1854 adev->mes.master_xcc_ids[xcc_id] =
1858 adev->mes.enable_coop_mode = 0;
1872 if (adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready)
1896 mes_v12_1_enable_unmapped_doorbell_handling(&adev->mes, true, xcc_id);
1902 r = mes_v12_1_set_hw_resources(&adev->mes,
1908 mes_v12_1_set_hw_resources_1(&adev->mes,
1911 mes_v12_1_init_aggregated_doorbell(&adev->mes, xcc_id);
1913 r = mes_v12_1_query_sched_status(&adev->mes,
1928 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = true;
1971 adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE;
1972 adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET;
1989 if (adev->mes.enable_coop_mode)
1994 if (adev->mes.enable_coop_mode &&
1995 adev->mes.master_xcc_ids[xcc_id] != xcc_id)
2083 if (!adev->mes.enable_coop_mode) {
2088 if (adev->mes.master_xcc_ids[i] == xcc_id)
2125 if (!adev->mes.enable_coop_mode) {
2130 if (xcc_id != adev->mes.master_xcc_ids[j])
2151 dev_err(adev->dev, "xcc%d: mes self test (%s) failed\n", xcc_id,
2159 dev_info(adev->dev, "xcc%d: mes self test (%s) pass\n", xcc_id,
2189 /* extra one page size padding for mes fw */
2193 doorbell_idx = adev->mes.db_start_dw_offset + \
2196 doorbell_idx = adev->mes.db_start_dw_offset + \
2200 if (adev->mes.enable_coop_mode &&
2203 if (adev->mes.master_xcc_ids[i] == xcc_id)
2250 r = mes_v12_1_add_hw_queue(&adev->mes, &add_queue);
2263 r = mes_v12_1_remove_hw_queue(&adev->mes, &remove_queue);