1083 	struct v11_compute_mqd *mqd = ring->mqd_ptr;  in mes_v11_0_mqd_init()  local
1087 	memset(mqd, 0, sizeof(*mqd));  in mes_v11_0_mqd_init()
1089 	mqd->header = 0xC0310800;  in mes_v11_0_mqd_init()
1090 	mqd->compute_pipelinestat_enable = 0x00000001;  in mes_v11_0_mqd_init()
1091 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in mes_v11_0_mqd_init()
1092 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in mes_v11_0_mqd_init()
1093 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in mes_v11_0_mqd_init()
1094 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in mes_v11_0_mqd_init()
1095 	mqd->compute_misc_reserved = 0x00000007;  in mes_v11_0_mqd_init()
1104 	mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);  in mes_v11_0_mqd_init()
1105 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);  in mes_v11_0_mqd_init()
1106 	mqd->cp_hqd_eop_control = tmp;  in mes_v11_0_mqd_init()
1110 	mqd->cp_hqd_pq_rptr = 0;  in mes_v11_0_mqd_init()
1111 	mqd->cp_hqd_pq_wptr_lo = 0;  in mes_v11_0_mqd_init()
1112 	mqd->cp_hqd_pq_wptr_hi = 0;  in mes_v11_0_mqd_init()
1115 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;  in mes_v11_0_mqd_init()
1116 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);  in mes_v11_0_mqd_init()
1121 	mqd->cp_mqd_control = tmp;  in mes_v11_0_mqd_init()
1125 	mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);  in mes_v11_0_mqd_init()
1126 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in mes_v11_0_mqd_init()
1130 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in mes_v11_0_mqd_init()
1131 	mqd->cp_hqd_pq_rptr_report_addr_hi =  in mes_v11_0_mqd_init()
1136 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;  in mes_v11_0_mqd_init()
1137 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in mes_v11_0_mqd_init()
1150 	mqd->cp_hqd_pq_control = tmp;  in mes_v11_0_mqd_init()
1166 	mqd->cp_hqd_pq_doorbell_control = tmp;  in mes_v11_0_mqd_init()
1168 	mqd->cp_hqd_vmid = 0;  in mes_v11_0_mqd_init()
1170 	mqd->cp_hqd_active = 1;  in mes_v11_0_mqd_init()
1175 	mqd->cp_hqd_persistent_state = tmp;  in mes_v11_0_mqd_init()
1177 	mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;  in mes_v11_0_mqd_init()
1178 	mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;  in mes_v11_0_mqd_init()
1179 	mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;  in mes_v11_0_mqd_init()
1187 	struct v11_compute_mqd *mqd = ring->mqd_ptr;  in mes_v11_0_queue_init_register()  local
1206 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);  in mes_v11_0_queue_init_register()
1207 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);  in mes_v11_0_queue_init_register()
1215 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);  in mes_v11_0_queue_init_register()
1216 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);  in mes_v11_0_queue_init_register()
1220 		     mqd->cp_hqd_pq_rptr_report_addr_lo);  in mes_v11_0_queue_init_register()
1222 		     mqd->cp_hqd_pq_rptr_report_addr_hi);  in mes_v11_0_queue_init_register()
1225 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);  in mes_v11_0_queue_init_register()
1229 		     mqd->cp_hqd_pq_wptr_poll_addr_lo);  in mes_v11_0_queue_init_register()
1231 		     mqd->cp_hqd_pq_wptr_poll_addr_hi);  in mes_v11_0_queue_init_register()
1235 		     mqd->cp_hqd_pq_doorbell_control);  in mes_v11_0_queue_init_register()
1238 	WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);  in mes_v11_0_queue_init_register()
1241 	WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);  in mes_v11_0_queue_init_register()