Lines Matching full:ring
61 * Set ring and irq function pointers
86 struct amdgpu_ring *ring; in jpeg_v2_0_sw_init() local
103 ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_sw_init()
104 ring->use_doorbell = true; in jpeg_v2_0_sw_init()
105 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; in jpeg_v2_0_sw_init()
106 ring->vm_hub = AMDGPU_MMHUB0(0); in jpeg_v2_0_sw_init()
107 sprintf(ring->name, "jpeg_dec"); in jpeg_v2_0_sw_init()
108 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v2_0_sw_init()
161 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_hw_init() local
163 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in jpeg_v2_0_hw_init()
166 return amdgpu_ring_test_helper(ring); in jpeg_v2_0_hw_init()
174 * Stop the JPEG block, mark ring as not ready any more
337 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_start() local
365 lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
367 upper_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
371 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v2_0_start()
372 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_start()
410 * @ring: amdgpu_ring pointer
414 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_get_rptr() argument
416 struct amdgpu_device *adev = ring->adev; in jpeg_v2_0_dec_ring_get_rptr()
424 * @ring: amdgpu_ring pointer
428 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_get_wptr() argument
430 struct amdgpu_device *adev = ring->adev; in jpeg_v2_0_dec_ring_get_wptr()
432 if (ring->use_doorbell) in jpeg_v2_0_dec_ring_get_wptr()
433 return *ring->wptr_cpu_addr; in jpeg_v2_0_dec_ring_get_wptr()
441 * @ring: amdgpu_ring pointer
445 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_set_wptr() argument
447 struct amdgpu_device *adev = ring->adev; in jpeg_v2_0_dec_ring_set_wptr()
449 if (ring->use_doorbell) { in jpeg_v2_0_dec_ring_set_wptr()
450 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); in jpeg_v2_0_dec_ring_set_wptr()
451 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
453 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
460 * @ring: amdgpu_ring pointer
462 * Write a start command to the ring.
464 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_insert_start() argument
466 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_start()
468 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
470 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_start()
472 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
478 * @ring: amdgpu_ring pointer
480 * Write a end command to the ring.
482 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_insert_end() argument
484 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_end()
486 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
488 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_end()
490 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
496 * @ring: amdgpu_ring pointer
501 * Write a fence and a trap command to the ring.
503 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in jpeg_v2_0_dec_ring_emit_fence() argument
508 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
510 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
512 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
514 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
516 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
518 amdgpu_ring_write(ring, lower_32_bits(addr)); in jpeg_v2_0_dec_ring_emit_fence()
520 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
522 amdgpu_ring_write(ring, upper_32_bits(addr)); in jpeg_v2_0_dec_ring_emit_fence()
524 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
526 amdgpu_ring_write(ring, 0x8); in jpeg_v2_0_dec_ring_emit_fence()
528 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
530 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
532 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
534 amdgpu_ring_write(ring, 0x3fbc); in jpeg_v2_0_dec_ring_emit_fence()
536 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_fence()
538 amdgpu_ring_write(ring, 0x1); in jpeg_v2_0_dec_ring_emit_fence()
540 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v2_0_dec_ring_emit_fence()
541 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
547 * @ring: amdgpu_ring pointer
552 * Write ring commands to execute the indirect buffer.
554 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, in jpeg_v2_0_dec_ring_emit_ib() argument
561 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
563 amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT)); in jpeg_v2_0_dec_ring_emit_ib()
565 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
568 if (ring->funcs->parse_cs) in jpeg_v2_0_dec_ring_emit_ib()
569 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_ib()
571 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); in jpeg_v2_0_dec_ring_emit_ib()
573 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
575 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); in jpeg_v2_0_dec_ring_emit_ib()
577 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
579 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
581 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
583 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
585 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
587 amdgpu_ring_write(ring, ib->length_dw); in jpeg_v2_0_dec_ring_emit_ib()
589 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
591 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
593 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
595 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
597 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); in jpeg_v2_0_dec_ring_emit_ib()
598 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_ib()
600 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
602 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_ib()
604 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
606 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
608 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
610 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
613 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, in jpeg_v2_0_dec_ring_emit_reg_wait() argument
618 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_reg_wait()
620 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_reg_wait()
622 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_reg_wait()
624 amdgpu_ring_write(ring, val); in jpeg_v2_0_dec_ring_emit_reg_wait()
626 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_reg_wait()
629 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_reg_wait()
630 amdgpu_ring_write(ring, in jpeg_v2_0_dec_ring_emit_reg_wait()
633 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_reg_wait()
634 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_reg_wait()
637 amdgpu_ring_write(ring, mask); in jpeg_v2_0_dec_ring_emit_reg_wait()
640 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, in jpeg_v2_0_dec_ring_emit_vm_flush() argument
643 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; in jpeg_v2_0_dec_ring_emit_vm_flush()
646 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in jpeg_v2_0_dec_ring_emit_vm_flush()
652 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); in jpeg_v2_0_dec_ring_emit_vm_flush()
655 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) in jpeg_v2_0_dec_ring_emit_wreg() argument
659 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_wreg()
662 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_wreg()
663 amdgpu_ring_write(ring, in jpeg_v2_0_dec_ring_emit_wreg()
666 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_wreg()
667 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_wreg()
670 amdgpu_ring_write(ring, val); in jpeg_v2_0_dec_ring_emit_wreg()
673 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) in jpeg_v2_0_dec_ring_nop() argument
677 WARN_ON(ring->wptr % 2 || count % 2); in jpeg_v2_0_dec_ring_nop()
680 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v2_0_dec_ring_nop()
681 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_nop()
769 static int jpeg_v2_0_ring_reset(struct amdgpu_ring *ring, in jpeg_v2_0_ring_reset() argument
775 amdgpu_ring_reset_helper_begin(ring, timedout_fence); in jpeg_v2_0_ring_reset()
776 r = jpeg_v2_0_stop(ring->adev); in jpeg_v2_0_ring_reset()
779 r = jpeg_v2_0_start(ring->adev); in jpeg_v2_0_ring_reset()
782 return amdgpu_ring_reset_helper_end(ring, timedout_fence); in jpeg_v2_0_ring_reset()