37 static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring);
42 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_…  in jpeg_v1_0_decode_ring_patch_wreg()  argument
44 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_patch_wreg()
45 …ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACK…  in jpeg_v1_0_decode_ring_patch_wreg()
48 		ring->ring[(*ptr)++] = 0;  in jpeg_v1_0_decode_ring_patch_wreg()
49 		ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);  in jpeg_v1_0_decode_ring_patch_wreg()
51 		ring->ring[(*ptr)++] = reg_offset;  in jpeg_v1_0_decode_ring_patch_wreg()
52 		ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);  in jpeg_v1_0_decode_ring_patch_wreg()
54 	ring->ring[(*ptr)++] = val;  in jpeg_v1_0_decode_ring_patch_wreg()
57 static void jpeg_v1_0_decode_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)  in jpeg_v1_0_decode_ring_set_patch_ring()  argument
59 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_set_patch_ring()
66 	val = lower_32_bits(ring->gpu_addr);  in jpeg_v1_0_decode_ring_set_patch_ring()
67 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);  in jpeg_v1_0_decode_ring_set_patch_ring()
72 	val = upper_32_bits(ring->gpu_addr);  in jpeg_v1_0_decode_ring_set_patch_ring()
73 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);  in jpeg_v1_0_decode_ring_set_patch_ring()
77 		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);  in jpeg_v1_0_decode_ring_set_patch_ring()
78 		ring->ring[ptr++] = 0;  in jpeg_v1_0_decode_ring_set_patch_ring()
85 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);  in jpeg_v1_0_decode_ring_set_patch_ring()
91 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);  in jpeg_v1_0_decode_ring_set_patch_ring()
99 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_…  in jpeg_v1_0_decode_ring_set_patch_ring()
100 	ring->ring[ptr++] = 0x01400200;  in jpeg_v1_0_decode_ring_set_patch_ring()
101 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0…  in jpeg_v1_0_decode_ring_set_patch_ring()
102 	ring->ring[ptr++] = val;  in jpeg_v1_0_decode_ring_set_patch_ring()
103 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ…  in jpeg_v1_0_decode_ring_set_patch_ring()
106 		ring->ring[ptr++] = 0;  in jpeg_v1_0_decode_ring_set_patch_ring()
107 		ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);  in jpeg_v1_0_decode_ring_set_patch_ring()
109 		ring->ring[ptr++] = reg_offset;  in jpeg_v1_0_decode_ring_set_patch_ring()
110 		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);  in jpeg_v1_0_decode_ring_set_patch_ring()
112 	ring->ring[ptr++] = mask;  in jpeg_v1_0_decode_ring_set_patch_ring()
116 		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);  in jpeg_v1_0_decode_ring_set_patch_ring()
117 		ring->ring[ptr++] = 0;  in jpeg_v1_0_decode_ring_set_patch_ring()
124 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);  in jpeg_v1_0_decode_ring_set_patch_ring()
130 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);  in jpeg_v1_0_decode_ring_set_patch_ring()
136  * @ring: amdgpu_ring pointer
140 static uint64_t jpeg_v1_0_decode_ring_get_rptr(struct amdgpu_ring *ring)  in jpeg_v1_0_decode_ring_get_rptr()  argument
142 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_get_rptr()
150  * @ring: amdgpu_ring pointer
154 static uint64_t jpeg_v1_0_decode_ring_get_wptr(struct amdgpu_ring *ring)  in jpeg_v1_0_decode_ring_get_wptr()  argument
156 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_get_wptr()
164  * @ring: amdgpu_ring pointer
168 static void jpeg_v1_0_decode_ring_set_wptr(struct amdgpu_ring *ring)  in jpeg_v1_0_decode_ring_set_wptr()  argument
170 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_set_wptr()
172 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));  in jpeg_v1_0_decode_ring_set_wptr()
178  * @ring: amdgpu_ring pointer
180  * Write a start command to the ring.
182 static void jpeg_v1_0_decode_ring_insert_start(struct amdgpu_ring *ring)  in jpeg_v1_0_decode_ring_insert_start()  argument
184 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_insert_start()
186 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_insert_start()
188 	amdgpu_ring_write(ring, 0x68e04);  in jpeg_v1_0_decode_ring_insert_start()
190 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));  in jpeg_v1_0_decode_ring_insert_start()
191 	amdgpu_ring_write(ring, 0x80010000);  in jpeg_v1_0_decode_ring_insert_start()
197  * @ring: amdgpu_ring pointer
199  * Write a end command to the ring.
201 static void jpeg_v1_0_decode_ring_insert_end(struct amdgpu_ring *ring)  in jpeg_v1_0_decode_ring_insert_end()  argument
203 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_insert_end()
205 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_insert_end()
207 	amdgpu_ring_write(ring, 0x68e04);  in jpeg_v1_0_decode_ring_insert_end()
209 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));  in jpeg_v1_0_decode_ring_insert_end()
210 	amdgpu_ring_write(ring, 0x00010000);  in jpeg_v1_0_decode_ring_insert_end()
216  * @ring: amdgpu_ring pointer
221  * Write a fence and a trap command to the ring.
223 static void jpeg_v1_0_decode_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,  in jpeg_v1_0_decode_ring_emit_fence()  argument
226 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_emit_fence()
230 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
232 	amdgpu_ring_write(ring, seq);  in jpeg_v1_0_decode_ring_emit_fence()
234 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
236 	amdgpu_ring_write(ring, seq);  in jpeg_v1_0_decode_ring_emit_fence()
238 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
240 	amdgpu_ring_write(ring, lower_32_bits(addr));  in jpeg_v1_0_decode_ring_emit_fence()
242 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
244 	amdgpu_ring_write(ring, upper_32_bits(addr));  in jpeg_v1_0_decode_ring_emit_fence()
246 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
248 	amdgpu_ring_write(ring, 0x8);  in jpeg_v1_0_decode_ring_emit_fence()
250 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
252 	amdgpu_ring_write(ring, 0);  in jpeg_v1_0_decode_ring_emit_fence()
254 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
256 	amdgpu_ring_write(ring, 0x01400200);  in jpeg_v1_0_decode_ring_emit_fence()
258 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
260 	amdgpu_ring_write(ring, seq);  in jpeg_v1_0_decode_ring_emit_fence()
262 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
264 	amdgpu_ring_write(ring, lower_32_bits(addr));  in jpeg_v1_0_decode_ring_emit_fence()
266 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
268 	amdgpu_ring_write(ring, upper_32_bits(addr));  in jpeg_v1_0_decode_ring_emit_fence()
270 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
272 	amdgpu_ring_write(ring, 0xffffffff);  in jpeg_v1_0_decode_ring_emit_fence()
274 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
276 	amdgpu_ring_write(ring, 0x3fbc);  in jpeg_v1_0_decode_ring_emit_fence()
278 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_fence()
280 	amdgpu_ring_write(ring, 0x1);  in jpeg_v1_0_decode_ring_emit_fence()
283 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));  in jpeg_v1_0_decode_ring_emit_fence()
284 	amdgpu_ring_write(ring, 0);  in jpeg_v1_0_decode_ring_emit_fence()
290  * @ring: amdgpu_ring pointer
295  * Write ring commands to execute the indirect buffer.
297 static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring,  in jpeg_v1_0_decode_ring_emit_ib()  argument
302 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_emit_ib()
305 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
307 	if (ring->funcs->parse_cs)  in jpeg_v1_0_decode_ring_emit_ib()
308 		amdgpu_ring_write(ring, 0);  in jpeg_v1_0_decode_ring_emit_ib()
310 		amdgpu_ring_write(ring, (vmid | (vmid << 4)));  in jpeg_v1_0_decode_ring_emit_ib()
312 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
314 	amdgpu_ring_write(ring, (vmid | (vmid << 4)));  in jpeg_v1_0_decode_ring_emit_ib()
316 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
318 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));  in jpeg_v1_0_decode_ring_emit_ib()
320 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
322 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in jpeg_v1_0_decode_ring_emit_ib()
324 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
326 	amdgpu_ring_write(ring, ib->length_dw);  in jpeg_v1_0_decode_ring_emit_ib()
328 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
330 	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));  in jpeg_v1_0_decode_ring_emit_ib()
332 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
334 	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));  in jpeg_v1_0_decode_ring_emit_ib()
336 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
338 	amdgpu_ring_write(ring, 0);  in jpeg_v1_0_decode_ring_emit_ib()
340 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
342 	amdgpu_ring_write(ring, 0x01400200);  in jpeg_v1_0_decode_ring_emit_ib()
344 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
346 	amdgpu_ring_write(ring, 0x2);  in jpeg_v1_0_decode_ring_emit_ib()
348 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_ib()
350 	amdgpu_ring_write(ring, 0x2);  in jpeg_v1_0_decode_ring_emit_ib()
353 static void jpeg_v1_0_decode_ring_emit_reg_wait(struct amdgpu_ring *ring,  in jpeg_v1_0_decode_ring_emit_reg_wait()  argument
357 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_emit_reg_wait()
360 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_reg_wait()
362 	amdgpu_ring_write(ring, 0x01400200);  in jpeg_v1_0_decode_ring_emit_reg_wait()
364 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_reg_wait()
366 	amdgpu_ring_write(ring, val);  in jpeg_v1_0_decode_ring_emit_reg_wait()
368 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_reg_wait()
372 		amdgpu_ring_write(ring, 0);  in jpeg_v1_0_decode_ring_emit_reg_wait()
373 		amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_reg_wait()
376 		amdgpu_ring_write(ring, reg_offset);  in jpeg_v1_0_decode_ring_emit_reg_wait()
377 		amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_reg_wait()
380 	amdgpu_ring_write(ring, mask);  in jpeg_v1_0_decode_ring_emit_reg_wait()
383 static void jpeg_v1_0_decode_ring_emit_vm_flush(struct amdgpu_ring *ring,  in jpeg_v1_0_decode_ring_emit_vm_flush()  argument
386 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];  in jpeg_v1_0_decode_ring_emit_vm_flush()
389 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);  in jpeg_v1_0_decode_ring_emit_vm_flush()
395 	jpeg_v1_0_decode_ring_emit_reg_wait(ring, data0, data1, mask);  in jpeg_v1_0_decode_ring_emit_vm_flush()
398 static void jpeg_v1_0_decode_ring_emit_wreg(struct amdgpu_ring *ring,  in jpeg_v1_0_decode_ring_emit_wreg()  argument
401 	struct amdgpu_device *adev = ring->adev;  in jpeg_v1_0_decode_ring_emit_wreg()
404 	amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_wreg()
408 		amdgpu_ring_write(ring, 0);  in jpeg_v1_0_decode_ring_emit_wreg()
409 		amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_wreg()
412 		amdgpu_ring_write(ring, reg_offset);  in jpeg_v1_0_decode_ring_emit_wreg()
413 		amdgpu_ring_write(ring,  in jpeg_v1_0_decode_ring_emit_wreg()
416 	amdgpu_ring_write(ring, val);  in jpeg_v1_0_decode_ring_emit_wreg()
419 static void jpeg_v1_0_decode_ring_nop(struct amdgpu_ring *ring, uint32_t count)  in jpeg_v1_0_decode_ring_nop()  argument
423 	WARN_ON(ring->wptr % 2 || count % 2);  in jpeg_v1_0_decode_ring_nop()
426 		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));  in jpeg_v1_0_decode_ring_nop()
427 		amdgpu_ring_write(ring, 0);  in jpeg_v1_0_decode_ring_nop()
463  * Set ring and irq function pointers
487 	struct amdgpu_ring *ring;  in jpeg_v1_0_sw_init()  local
495 	ring = adev->jpeg.inst->ring_dec;  in jpeg_v1_0_sw_init()
496 	ring->vm_hub = AMDGPU_MMHUB0(0);  in jpeg_v1_0_sw_init()
497 	sprintf(ring->name, "jpeg_dec");  in jpeg_v1_0_sw_init()
498 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,  in jpeg_v1_0_sw_init()
533 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;  in jpeg_v1_0_start()  local
539 		WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));  in jpeg_v1_0_start()
540 		WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));  in jpeg_v1_0_start()
547 	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);  in jpeg_v1_0_start()
549 	/* copy patch commands to the jpeg ring */  in jpeg_v1_0_start()
550 	jpeg_v1_0_decode_ring_set_patch_ring(ring,  in jpeg_v1_0_start()
551 		(ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));  in jpeg_v1_0_start()
604 static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring)  in jpeg_v1_0_ring_begin_use()  argument
606 	struct	amdgpu_device *adev = ring->adev;  in jpeg_v1_0_ring_begin_use()
613 		DRM_ERROR("JPEG dec: vcn dec ring may not be empty\n");  in jpeg_v1_0_ring_begin_use()
617 			DRM_ERROR("JPEG dec: vcn enc ring[%d] may not be empty\n", cnt);  in jpeg_v1_0_ring_begin_use()
620 	vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);  in jpeg_v1_0_ring_begin_use()