26 #include "hdp/hdp_5_0_0_offset.h"
27 #include "hdp/hdp_5_0_0_sh_mask.h"
34 		WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);  in hdp_v5_0_invalidate_hdp()
35 		RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);  in hdp_v5_0_invalidate_hdp()
38 					HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);  in hdp_v5_0_invalidate_hdp()
53 	hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);  in hdp_v5_0_update_mem_power_gating()
54 	hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);  in hdp_v5_0_update_mem_power_gating()
62 	WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);  in hdp_v5_0_update_mem_power_gating()
64 	/* HDP 5.0 doesn't support dynamic power mode switch,  in hdp_v5_0_update_mem_power_gating()
82 	WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);  in hdp_v5_0_update_mem_power_gating()
124 			WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);  in hdp_v5_0_update_mem_power_gating()
133 	WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);  in hdp_v5_0_update_mem_power_gating()
144 	hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);  in hdp_v5_0_update_medium_grain_clock_gating()
164 	WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);  in hdp_v5_0_update_medium_grain_clock_gating()
180 	tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);  in hdp_v5_0_get_clockgating_state()
190 	tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);  in hdp_v5_0_get_clockgating_state()
203 	tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);  in hdp_v5_0_init_registers()
205 	WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);  in hdp_v5_0_init_registers()