27 #include "hdp/hdp_4_0_offset.h"
28 #include "hdp/hdp_4_0_sh_mask.h"
48 		WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);  in hdp_v4_0_invalidate_hdp()
49 		RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);  in hdp_v4_0_invalidate_hdp()
52 			HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);  in hdp_v4_0_invalidate_hdp()
67 	/* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */  in hdp_v4_0_query_ras_error_count()
68 	err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);  in hdp_v4_0_query_ras_error_count()
77 		WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);  in hdp_v4_0_reset_ras_error_count()
79 		/*read back hdp ras counter to reset it to 0 */  in hdp_v4_0_reset_ras_error_count()
80 		RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);  in hdp_v4_0_reset_ras_error_count()
92 		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));  in hdp_v4_0_update_clock_gating()
100 			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);  in hdp_v4_0_update_clock_gating()
102 		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));  in hdp_v4_0_update_clock_gating()
116 			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);  in hdp_v4_0_update_clock_gating()
132 	data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));  in hdp_v4_0_get_clockgating_state()
141 		WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);  in hdp_v4_0_init_registers()
151 	WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);  in hdp_v4_0_init_registers()
154 		WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);  in hdp_v4_0_init_registers()
156 	WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));  in hdp_v4_0_init_registers()
157 	WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));  in hdp_v4_0_init_registers()