Lines Matching full:gmc

166 	adev->gmc.vm_fault.num_types = 1;
167 	adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;
170 		adev->gmc.ecc_irq.num_types = 1;
171 		adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;
244 	spin_lock(&adev->gmc.invalidate_lock);
295 	spin_unlock(&adev->gmc.invalidate_lock);
458 	if (!adev->gmc.translate_further)
538 	adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs;
612 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
613 	adev->gmc.shared_aperture_end =
614 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
615 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;
616 	adev->gmc.private_aperture_end =
617 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;
618 	adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
636 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
647 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);
675 	adev->gmc.mc_vram_size =
677 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
684 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
685 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
689 		adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
690 		adev->gmc.aper_size = adev->gmc.real_vram_size;
694 	adev->gmc.visible_vram_size = adev->gmc.aper_size;
695 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
696 		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
700 		adev->gmc.gart_size = 512ULL << 20;
702 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
704 	gmc_v11_0_vram_gtt_location(adev, &adev->gmc);
739 	spin_lock_init(&adev->gmc.invalidate_lock);
743 	adev->gmc.vram_width = vram_width;
745 	adev->gmc.vram_type = vram_type;
746 	adev->gmc.vram_vendor = vram_vendor;
754 		adev->gmc.mall_size *= 2;
786 			      &adev->gmc.vm_fault);
793 			      &adev->gmc.vm_fault);
800 				      &adev->gmc.ecc_irq);
809 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
916 		 (unsigned int)(adev->gmc.gart_size >> 20),
927 	adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode;
959 		/* full access mode, so don't touch any GMC register */
964 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
966 	if (adev->gmc.ecc_irq.funcs &&
968 		amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
997 	/* MC is always ready in GMC v11.*/
1003 	/* There is no need to wait for MC idle in GMC v11.*/