Lines Matching full:gart
237 * GART
244 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
259 /* Use register 17 for GART */ in gmc_v10_0_flush_gpu_tlb()
703 * vram and gart within the GPU's physical address space.
732 /* set the gart size */ in gmc_v10_0_mc_init()
758 if (adev->gart.bo) { in gmc_v10_0_gart_init()
759 WARN(1, "NAVI10 PCIE GART already initialized\n"); in gmc_v10_0_gart_init()
763 /* Initialize common gart structure */ in gmc_v10_0_gart_init()
768 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v10_0_gart_init()
769 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | in gmc_v10_0_gart_init()
919 * Tears down the driver GART/VM setup (CIK).
943 * gmc_v10_0_gart_enable - gart enable
952 if (adev->gart.bo == NULL) { in gmc_v10_0_gart_enable()
953 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v10_0_gart_enable()
984 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in gmc_v10_0_gart_enable()
986 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); in gmc_v10_0_gart_enable()
1025 * gmc_v10_0_gart_disable - gart disable