Lines Matching refs:tmp
128 uint32_t tmp; in gfxhub_v1_2_xcc_init_system_aperture_regs() local
174 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2); in gfxhub_v1_2_xcc_init_system_aperture_regs()
175 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v1_2_xcc_init_system_aperture_regs()
177 WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp); in gfxhub_v1_2_xcc_init_system_aperture_regs()
197 uint32_t tmp; in gfxhub_v1_2_xcc_init_tlb_regs() local
202 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_2_xcc_init_tlb_regs()
204 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
206 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
208 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
210 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
212 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
214 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_2_xcc_init_tlb_regs()
216 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_2_xcc_init_tlb_regs()
223 uint32_t tmp; in gfxhub_v1_2_xcc_init_cache_regs() local
228 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL); in gfxhub_v1_2_xcc_init_cache_regs()
229 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
230 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_2_xcc_init_cache_regs()
232 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_2_xcc_init_cache_regs()
234 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in gfxhub_v1_2_xcc_init_cache_regs()
235 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
236 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in gfxhub_v1_2_xcc_init_cache_regs()
237 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
239 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2); in gfxhub_v1_2_xcc_init_cache_regs()
240 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_2_xcc_init_cache_regs()
241 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
242 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
244 tmp = regVM_L2_CNTL3_DEFAULT; in gfxhub_v1_2_xcc_init_cache_regs()
246 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_2_xcc_init_cache_regs()
247 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_2_xcc_init_cache_regs()
250 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_2_xcc_init_cache_regs()
251 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_2_xcc_init_cache_regs()
254 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
256 tmp = regVM_L2_CNTL4_DEFAULT; in gfxhub_v1_2_xcc_init_cache_regs()
259 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); in gfxhub_v1_2_xcc_init_cache_regs()
260 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); in gfxhub_v1_2_xcc_init_cache_regs()
262 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); in gfxhub_v1_2_xcc_init_cache_regs()
263 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); in gfxhub_v1_2_xcc_init_cache_regs()
265 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
272 uint32_t tmp; in gfxhub_v1_2_xcc_enable_system_domain() local
276 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL); in gfxhub_v1_2_xcc_enable_system_domain()
277 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_2_xcc_enable_system_domain()
278 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_2_xcc_enable_system_domain()
280 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, in gfxhub_v1_2_xcc_enable_system_domain()
282 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in gfxhub_v1_2_xcc_enable_system_domain()
284 WREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL, tmp); in gfxhub_v1_2_xcc_enable_system_domain()
321 uint32_t tmp; in gfxhub_v1_2_xcc_setup_vmid_config() local
334 tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
336 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_2_xcc_setup_vmid_config()
337 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_2_xcc_setup_vmid_config()
339 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
341 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
344 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
346 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
348 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
350 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
352 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
354 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
362 tmp = REG_SET_FIELD( in gfxhub_v1_2_xcc_setup_vmid_config()
363 tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
375 i * hub->ctx_distance, tmp); in gfxhub_v1_2_xcc_setup_vmid_config()
443 u32 tmp; in gfxhub_v1_2_xcc_gart_disable() local
454 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_2_xcc_gart_disable()
455 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_2_xcc_gart_disable()
456 tmp = REG_SET_FIELD(tmp, in gfxhub_v1_2_xcc_gart_disable()
460 WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_2_xcc_gart_disable()
464 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL); in gfxhub_v1_2_xcc_gart_disable()
465 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_2_xcc_gart_disable()
466 WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp); in gfxhub_v1_2_xcc_gart_disable()
484 u32 tmp; in gfxhub_v1_2_xcc_set_fault_enable_default() local
488 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v1_2_xcc_set_fault_enable_default()
489 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
491 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
493 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
495 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
497 tmp = REG_SET_FIELD(tmp, in gfxhub_v1_2_xcc_set_fault_enable_default()
501 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
503 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
505 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
507 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
509 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
511 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
514 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
516 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
519 WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v1_2_xcc_set_fault_enable_default()