194 	uint32_t tmp;  in gfxhub_v12_0_init_tlb_regs()  local
197 	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v12_0_init_tlb_regs()
199 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v12_0_init_tlb_regs()
200 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v12_0_init_tlb_regs()
201 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v12_0_init_tlb_regs()
203 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v12_0_init_tlb_regs()
205 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);  in gfxhub_v12_0_init_tlb_regs()
206 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v12_0_init_tlb_regs()
209 	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v12_0_init_tlb_regs()
214 	uint32_t tmp;  in gfxhub_v12_0_init_cache_regs()  local
223 	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);  in gfxhub_v12_0_init_cache_regs()
224 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v12_0_init_cache_regs()
225 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);  in gfxhub_v12_0_init_cache_regs()
226 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v12_0_init_cache_regs()
229 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v12_0_init_cache_regs()
231 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);  in gfxhub_v12_0_init_cache_regs()
232 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v12_0_init_cache_regs()
233 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v12_0_init_cache_regs()
234 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);  in gfxhub_v12_0_init_cache_regs()
236 	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);  in gfxhub_v12_0_init_cache_regs()
237 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v12_0_init_cache_regs()
238 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v12_0_init_cache_regs()
239 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);  in gfxhub_v12_0_init_cache_regs()
241 	tmp = regGCVM_L2_CNTL3_DEFAULT;  in gfxhub_v12_0_init_cache_regs()
243 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v12_0_init_cache_regs()
244 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v12_0_init_cache_regs()
247 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v12_0_init_cache_regs()
248 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v12_0_init_cache_regs()
251 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);  in gfxhub_v12_0_init_cache_regs()
253 	tmp = regGCVM_L2_CNTL4_DEFAULT;  in gfxhub_v12_0_init_cache_regs()
254 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v12_0_init_cache_regs()
255 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v12_0_init_cache_regs()
256 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);  in gfxhub_v12_0_init_cache_regs()
258 	tmp = regGCVM_L2_CNTL5_DEFAULT;  in gfxhub_v12_0_init_cache_regs()
259 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);  in gfxhub_v12_0_init_cache_regs()
260 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);  in gfxhub_v12_0_init_cache_regs()
265 	uint32_t tmp;  in gfxhub_v12_0_enable_system_domain()  local
267 	tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);  in gfxhub_v12_0_enable_system_domain()
268 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v12_0_enable_system_domain()
269 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gfxhub_v12_0_enable_system_domain()
270 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,  in gfxhub_v12_0_enable_system_domain()
272 	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);  in gfxhub_v12_0_enable_system_domain()
302 	uint32_t tmp;  in gfxhub_v12_0_setup_vmid_config()  local
305 		tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);  in gfxhub_v12_0_setup_vmid_config()
306 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v12_0_setup_vmid_config()
307 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v12_0_setup_vmid_config()
309 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v12_0_setup_vmid_config()
311 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v12_0_setup_vmid_config()
313 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v12_0_setup_vmid_config()
315 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v12_0_setup_vmid_config()
317 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v12_0_setup_vmid_config()
319 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v12_0_setup_vmid_config()
321 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v12_0_setup_vmid_config()
323 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v12_0_setup_vmid_config()
327 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v12_0_setup_vmid_config()
331 				    i * hub->ctx_distance, tmp);  in gfxhub_v12_0_setup_vmid_config()
344 	hub->vm_cntx_cntl = tmp;  in gfxhub_v12_0_setup_vmid_config()
391 	u32 tmp;  in gfxhub_v12_0_gart_disable()  local
400 	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v12_0_gart_disable()
401 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v12_0_gart_disable()
402 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v12_0_gart_disable()
404 	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v12_0_gart_disable()
420 	u32 tmp;  in gfxhub_v12_0_set_fault_enable_default()  local
423 	tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);  in gfxhub_v12_0_set_fault_enable_default()
424 	tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);  in gfxhub_v12_0_set_fault_enable_default()
425 	WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);  in gfxhub_v12_0_set_fault_enable_default()
433 	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v12_0_set_fault_enable_default()
434 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
436 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
438 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
440 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
442 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
445 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
447 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
449 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
451 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
453 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
455 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
458 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
460 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v12_0_set_fault_enable_default()
463 	WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v12_0_set_fault_enable_default()