Lines Matching full:amdgpu
30 #include "amdgpu.h"
101 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
102 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
103 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
104 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
105 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
106 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
108 MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
109 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
110 MODULE_FIRMWARE("amdgpu/stoney_me.bin");
111 MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
112 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
114 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
115 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
116 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
117 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
118 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
119 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
121 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
122 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
123 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
124 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
125 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
127 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
128 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
129 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
130 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
131 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
132 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
134 MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
135 MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
136 MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
137 MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
138 MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
139 MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
140 MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
141 MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
142 MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
143 MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
144 MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
146 MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
147 MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
148 MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
149 MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
150 MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
151 MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
152 MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
153 MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
154 MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
155 MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
156 MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
158 MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
159 MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
160 MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
161 MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
162 MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
163 MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
164 MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
165 MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
166 MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
167 MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
168 MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
170 MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
171 MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
172 MODULE_FIRMWARE("amdgpu/vegam_me.bin");
173 MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
174 MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
175 MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
986 "amdgpu/%s_pfp_2.bin", chip_name); in gfx_v8_0_init_microcode()
990 "amdgpu/%s_pfp.bin", chip_name); in gfx_v8_0_init_microcode()
995 "amdgpu/%s_pfp.bin", chip_name); in gfx_v8_0_init_microcode()
1006 "amdgpu/%s_me_2.bin", chip_name); in gfx_v8_0_init_microcode()
1010 "amdgpu/%s_me.bin", chip_name); in gfx_v8_0_init_microcode()
1015 "amdgpu/%s_me.bin", chip_name); in gfx_v8_0_init_microcode()
1027 "amdgpu/%s_ce_2.bin", chip_name); in gfx_v8_0_init_microcode()
1031 "amdgpu/%s_ce.bin", chip_name); in gfx_v8_0_init_microcode()
1036 "amdgpu/%s_ce.bin", chip_name); in gfx_v8_0_init_microcode()
1057 "amdgpu/%s_rlc.bin", chip_name); in gfx_v8_0_init_microcode()
1107 "amdgpu/%s_mec_2.bin", chip_name); in gfx_v8_0_init_microcode()
1111 "amdgpu/%s_mec.bin", chip_name); in gfx_v8_0_init_microcode()
1116 "amdgpu/%s_mec.bin", chip_name); in gfx_v8_0_init_microcode()
1129 "amdgpu/%s_mec2_2.bin", chip_name); in gfx_v8_0_init_microcode()
1133 "amdgpu/%s_mec2.bin", chip_name); in gfx_v8_0_init_microcode()
1138 "amdgpu/%s_mec2.bin", chip_name); in gfx_v8_0_init_microcode()
1539 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); in gfx_v8_0_do_edc_gpr_workarounds()
1634 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); in gfx_v8_0_do_edc_gpr_workarounds()
1641 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); in gfx_v8_0_do_edc_gpr_workarounds()
4168 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); in gfx_v8_0_cp_gfx_start()
6457 * amdgpu controls only the first MEC. That's why this function only in gfx_v8_0_set_compute_eop_interrupt_state()
6897 * amdgpu controls only 1st ME(0-3 CS pipes). in gfx_v8_0_emit_wave_limit()